Digital AGC for a CDMA radiotelephone

Claim 5

A method as set forth in claim 2 where the logarithm is the second logarithm of the power, and wherein the step of calculating includes the steps of: inputting a digital word that represents a value of the received integrated power to a priority encoder to determine a position of the most significant set bit of the digital word; extracting one or more bits that are adjacent to the determined most significant set bit; concatenating the extracted bit or bits to a binary value representing the determined position of the most significant set bit; and using the resulting concatenated bit or bits as an approximate value of the second logarithm.

Claim 6

A method as set forth in claim 2, and further including the steps of: generating a second counter value; subtracting the second counter value from the first counter value to form a second error signal; filtering the second error signal; comparing the filtered second error signal to a predetermined second threshold range; incrementing or decrementing the second counter value and resetting a filter accumulator as a function of the result of the step of comparing the filtered second error signal; and converting at least the second counter value to an analog voltage for controlling the gain of a transmitter.

Claim 7

A method as set forth in claim 2, and further comprising the steps of: generating a second counter value; subtracting the second counter value from the first counter value to form a second error signal; filtering the second error signal; comparing the filtered second error signal to a predetermined second threshold range; incrementing or decrementing the second counter value and resetting a filter accumulator as a function of the result of the step of comparing the filtered second error signal; setting a third counter value in accordance with power control command bits that are received from a base site transmitter; adding the second counter value to the third counter value to form a sum of the second and third counter values; and converting the sum of the second and third counter values to an analog voltage for controlling the gain of a transmitter.

Claim 8

A method as set forth in claim 5 wherein the step of converting the first counter value includes a preliminary step of applying an amplifier slope correction to the first counter value, and wherein the step of converting the sum of the second and third counter values includes a preliminary step of applying an amplifier slope correction to the sum of the second and third counter values.

Claim 9

Apparatus for generating a gain control signal for a transceiver, comprising: means for integrating the power of a received and sampled signal; means for calculating a logarithm of the received integrated power; means for subtracting a predetermined reference value from the logarithm of the power to generate a first error signal; means for filtering the first error signal; means for comparing the filtered first error signal to a predetermined first threshold; means for incrementing or decrementing a first counter value and resetting a filter accumulator as a function of an operation of said comparing means; and means for converting the first counter value to an analog voltage for controlling the gain of a receiver; where the logarithm is the second logarithm of the power, and wherein the calculating means includes: priority encoder means for inputting a digital word that represents a value of the received integrated power for determining a position of the most significant set bit of the digital word; wherein the determined position is designated as the second logarithm.

Claim 10

Apparatus for generating a gain control signal for a transceiver, comprising: means for integrating the power of a received and sampled signal; means for calculating a logarithm of the received integrated power; means for subtracting a predetermined reference value from the logarithm of the power to generate a first error signal; means for filtering the first error signal; means for comparing the filtered first error signal to a predetermined first threshold; means for incrementing or decrementing a first counter value and resetting a filter accumulator as a function of an operation of said comparing means; and means for converting the first counter value to an analog voltage for controlling the gain of a receiver; where the logarithm is the second logarithm of the power, and wherein the calculating means includes: priority encoder means for inputting a digital word that represents a value of the received integrated power for determining a position of the most significant set bit of the digital word; wherein the determined position is designated as the second logarithm.

Claim 11

Apparatus for generating a gain control signal for a transceiver, comprising: means for integrating the power of a received and sampled signal; means for calculating a logarithm of the received integrated power; means for subtracting a predetermined logarithmic power reference value from the logarithm of the power to generate a first error signal; means for filtering the first error signal; means for comparing the filtered first error signal to a predetermined first threshold range; means for incrementing or decrementing a first counter value and resetting a filter accumulator as a function of an operation of said comparing means; and means for converting the first counter value to an analog voltage for controlling the gain of a receiver.

Claim 12

Apparatus for generating a gain control signal for a transceiver, comprising: means for integrating the power of a received and sampled signal; means for calculating a logarithm of the received integrated power; means for subtracting a predetermined logarithmic power reference value from the logarithm of the power to generate a first error signal; means for filtering the first error signal; means for comparing the filtered first error signal to a predetermined first threshold range; means for incrementing or decrementing a first counter value and resetting a filter accumulator as a function of an operation of said comparing means; and means for converting the first counter value to an analog voltage for controlling the gain of a receiver.

Claim 13

Apparatus as set forth in claim 8 where the logarithm is the second logarithm of the power, and wherein said calculating means includes: priority encoder means for inputting a digital word that represents a value of the received integrated power for determining a position of the most significant set bit of the digital word; wherein the determined position is designated as the second logarithm; means for extracting one or more bits that are adjacent to the determined most significant set bit; and means for concatenating the extracted bit or bits to the determined most significant set bit; and wherein the resulting concatenated bits are designated as an approximate value of the second logarithm.

Claim 14

Apparatus as set forth in claim 8, and further comprising: means for generating a second counter value; means for subtracting the second counter value from the first counter value to form a second error signal; means for filtering the second error signal; means for comparing the filtered second error signal to a predetermined second threshold range; means for incrementing or decrementing the second counter value and resetting a filter accumulator as a function of an operation of said means for comparing the filtered second error signal; and means for converting at least the second counter value to an analog voltage for controlling the gain of a transmitter.

Claim 15

Apparatus as set forth in claim 8, and further comprising: means for generating a second counter value; means for subtracting the second counter value from the first counter value to form a second error signal; means for filtering the second error signal; means for comparing the filtered second error signal to a predetermined second threshold range; means for incrementing or decrementing the second counter value and for resetting a filter accumulator as a function of an operation of said means for comparing the filtered second error signal; means for setting a third counter value in accordance with power control command bits that are received from a base site transmitter; means for adding the second counter value to the third counter value to form a sum of the second and third counter values; and means for converting the sum of the second and third counter values to an analog voltage for controlling the gain of a transmitter.

Claim 16

Apparatus as set forth in claim 11 wherein said apparatus further includes means for applying an amplifier slope correction to the first counter value and to the sum of the second and third counter value.

Claim 19

A method as set forth in claim 13 wherein the step of squaring includes the steps of: converting each of the I and Q signals to a digital representation; alternately applying the digital representations to address inputs of a memory device; and for each application of one of the digital representations, outputting a value from the memory device that corresponds to a square of the digital representation.

Claim 20

A method as set forth in claim 13, and further including the steps of: generating a second counter value; subtracting the second counter value from the first counter value to form a second error signal; filtering the second error signal; comparing the filtered second error signal to a second bipolar threshold signal and incrementing or decrementing the second counter value and resetting a filter accumulator in accordance with the comparison to form an open loop transmitter power control value; combining the open loop power control value with a closed loop power control value to form a combined power control value; and generating a gain control signal for at least one transmitter amplifier in accordance with the combined power control value.

Claim 21

A method as set forth in claim 13, and further including the steps of: generating a second counter value; subtracting the second counter value from the first counter value and subtracting the derived indication of the power of the received signal over the period from a reference value to form a second error signal; filtering the second error signal; comparing the filtered second error signal to a second bipolar threshold signal and incrementing or decrementing the second counter value and resetting a filter accumulator in accordance with the comparison to form an open loop transmitter power control value; combining the open loop power control value with a closed loop power control value to form a combined power control value; and generating a gain control signal for at least one transmitter amplifier in accordance with the combined power control value.

Claim 22

A spread spectrum transceiver, comprising: a transmitter for transmitting a spread spectrum RF signal through at least one transmitter amplifier; a receiver for receiving a spread spectrum RF signal and for amplifying the received signal with at least one receiver amplifier; a demodulator for demodulating the amplified RF signal to derive in-phase I and quadrature Q signals; means for deriving from the I and Q signals an indication of the power of the received signal over a period; means for obtaining a first error signal that indicates a difference between the power indication and a predetermined power; a first filter for filtering the first error signal; means for comparing the filtered first error signal to a first threshold signal and for incrementing or decrementing a first value and for resetting a filter accumulator in accordance with the comparison; means for generating a gain control signal for the at least one receiver amplifier in accordance with the first value; means for generating a second value; means for subtracting the second value from the first value and for subtracting the derived indication of the power of the received signal over the period from a reference value to form a second error signal; a second filter for filtering the second error signal; means for comparing the filtered second error signal to a second threshold signal and for incrementing or decrementing the second value and for resetting a filter accumulator in accordance with the comparison to form an open loop transmitter power control value; means for combining the open loop power control value with a closed loop power control value to form a combined power control value; and means for generating a gain control signal for said at least one transmitter amplifier in accordance with the combined power control value.

Claim 23

A spread spectrum transceiver, comprising: a transmitter for transmitting a spread spectrum RF signal through at least one transmitter amplifier; a receiver for receiving a spread spectrum RF signal and for amplifying the received signal with at least one receiver amplifier; a demodulator for demodulating the amplified RF signal to derive in-phase I and quadrature Q signals; means for deriving from the I and Q signals an indication of the power of the received signal over a period; means for obtaining a first error signal that indicates a difference between the power indication and a predetermined power; a first filter for filtering the first error signal; means for comparing the filtered first error signal to a first threshold signal and for incrementing or decrementing a first value and for resetting a filter accumulator in accordance with the comparison; means for generating a gain control signal for the at least one receiver amplifier in accordance with the first value; means for generating a second value; means for subtracting the second value from the first value and for subtracting the derived indication of the power of the received signal over the period from a reference value to form a second error signal; a second filter for filtering the second error signal; means for comparing the filtered second error signal to a second threshold signal and for incrementing or decrementing the second value and for resetting a filter accumulator in accordance with the comparison to form an open loop transmitter power control value; means for combining the open loop power control value with a closed loop power control value to form a combined power control value; and means for generating a gain control signal for said at least one transmitter amplifier in accordance with the combined power control value.

Claim 24

A spread spectrum transceiver as set forth in claim 17 wherein said means for deriving is comprised of: means for repetitively squaring a magnitude of the I and Q signals; and means for integrating the squared magnitudes over the period to derive the indication of the power of the received signal over the period.

Claim 25

A spread spectrum transceiver as set forth in claim 17 wherein a step size in the value of said first value is equivalent to a value expressed in a predetermined number of dB, and wherein the derived indication of the power of the received signal over the period is a linear approximation of the power of the received signal over the period.

Claim 26

A spread spectrum transceiver as set forth in claim 19 wherein the difference between the derived indication of the power of the received signal over the period and the reference value causes the open loop transmitter power control value to be controlled with a resolution that is less than the predetermined number of dB.

Claim 27

A spread spectrum transceiver as set forth in claim 20 wherein the predetermined number of dB is one.

Claim 28

A spread spectrum transceiver as set forth in claim 17 wherein a value of the first threshold is a function of a desired step size in dB of the receiver gain control signal.

Claim 29

A spread spectrum transceiver as set forth in claim 17 wherein a value of the second threshold is a function of a desired step size in dB of the transmitter gain control signal.

Claim 30

A spread spectrum transceiver as set forth in claim 17 wherein a value of the first threshold, in dB, is approximately one half of a desired step size, in dB, of the receiver gain control signal.

Claim 31

A spread spectrum transceiver as set forth in claim 17 wherein a value of the first threshold is a function of a desired step size, in dB, of the receiver gain control signal, wherein a value of the second threshold is a function of a desired step size, in dB, of the transmitter gain control signal, and wherein the desired step size, in dB, of the transmitter gain control signal is less than the desired step size, in dB, of the receiver gain control signal.

Claim 32

A spread spectrum transceiver as set forth in claim 17 wherein the period is a symbol period.