US5564009A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Methods and apparatus for burst data block movement in a multi-tasking windows system
Assignee: Hewlett Packard Development Co LP
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Filing: 1995-06-02
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Granted: 1996-10-08
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Expires: 2015-06-02
Abstract
Abstract Graphics window systems which utilize graphics pipelines and graphics pipeline bypass buses. Hardware solutions for window relative rendering of graphics primitives, block moving of graphics primitives, transfer of large data blocks, and elimination of pipeline flushing are disclosed. The hardware implementations provided in accordance with the invention are interfaced along the pipeline bypass bus, thereby eliminating gross overhead processor time for the graphics pipeline and reducing pipeline latency. Methods and apparatus provided in accordance with the invention exhibit significant pipeline efficiency and reductions in time to render graphics primitives to the screen system.
Inventors
- 👤 David Pinedo
- 👤 Darel N. Emmot
- 👤 Ronald D. Larson
- 👤 Byron A. Alcorn
- 👤 Desi Rhoden
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 17:02
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/14; G09G5/36; G09G5/39; G09G5/393; G09G2360/00; G09G2360/12; G09G2360/121
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
171 words
A computer system of the type employing a host, a frame buffer, and a pipeline graphics processor, for optimizing a bandwidth between the host and the frame buffer, for providing a high speed path between the frame buffer and the host, and for providing a source reference address or a destination reference address in a memory of the host where the host is operatively coupled to the pipeline graphics processor and the pipeline graphics processor is operatively coupled to the frame buffer, the system comprising: a pipeline bypass where the pipeline bypass is operatively coupled to the host and the frame buffer; burst data block means having at least one data register interposed on the frame buffer for directly storing data blocks received from the host; block moving means interfaced with the data register for rendering the data blocks to the frame buffer; and alignment register means interfaced with the block moving means for defining a sub-block and for clipping data rendered to the frame buffer which falls outside the sub-block.
Claim 2
Dependent Claim
171 words
A computer system of the type employing a host, a frame buffer, and a pipeline graphics processor, for optimizing a bandwidth between the host and the frame buffer, for providing a high speed path between the frame buffer and the host, and for providing a source reference address or a destination reference address in a memory of the host where the host is operatively coupled to the pipeline graphics processor and the pipeline graphics processor is operatively coupled to the frame buffer, the system comprising: a pipeline bypass where the pipeline bypass is operatively coupled to the host and the frame buffer; burst data block means having at least one data register interposed on the frame buffer for directly storing data blocks received from the host; block moving means interfaced with the data register for rendering the data blocks to the frame buffer; and alignment register means interfaced with the block moving means for defining a sub-block and for clipping data rendered to the frame buffer which falls outside the sub-block.
Claim 3
Dependent Claim
174 words
A computer system of the type employing a host, a frame buffer, and a pipeline graphics processor, for optimizing a bandwidth between the host and the frame buffer, for providing a high speed path between the frame buffer and the host, and for providing a source reference address or a destination reference address in a memory of the host where the host is operatively coupled to the pipeline graphics processor and the pipeline graphics processor is operatively coupled to the frame buffer, the system comprising: a pipeline bypass where the pipeline bypass is operatively coupled to the host and the frame buffer; burst data block means having at least one data register interposed on the pipeline bypass for directly storing data blocks received from the host; block moving means interfaced with the data register for transmitting the data blocks from the frame buffer, to the host; and alignment register means interfaced with the block moving means for defining a sub-block and for clipping data rendered to the frame buffer which falls outside the sub-block.
Claim 4
Dependent Claim
174 words
A computer system of the type employing a host, a frame buffer, and a pipeline graphics processor, for optimizing a bandwidth between the host and the frame buffer, for providing a high speed path between the frame buffer and the host, and for providing a source reference address or a destination reference address in a memory of the host where the host is operatively coupled to the pipeline graphics processor and the pipeline graphics processor is operatively coupled to the frame buffer, the system comprising: a pipeline bypass where the pipeline bypass is operatively coupled to the host and the frame buffer; burst data block means having at least one data register interposed on the pipeline bypass for directly storing data blocks received from the host; block moving means interfaced with the data register for transmitting the data blocks from the frame buffer, to the host; and alignment register means interfaced with the block moving means for defining a sub-block and for clipping data rendered to the frame buffer which falls outside the sub-block.
Claim 5
Dependent Claim
19 words
The system recited in claim 2 wherein the at least one data register is a first-in, first-out data register.
Claim 6
Dependent Claim
21 words
The system recited in claim 3 wherein the at least one data register comprises a plurality of first-in, first-out data registers.
Claim 7
Dependent Claim
16 words
The system recited in claim 4 wherein the frame buffer is a video random access memory.
Claim 8
Dependent Claim
21 words
The system recited in claim 5 wherein the data blocks stored in the at least one data register are graphics primitives.
Claim 9
Independent Claim
130 words
A system for transferring blocks directly from a host to a frame buffer comprising: pipeline bypass means interfaced with the host and the frame buffer for bussing data; burst data block means interposed on the pipeline bypass means for receiving data blocks from the host and for transmitting data blocks from the host to the frame buffer; address register means interfaced with the host for receiving block reference addresses and block size data from the host; block moving means interfaced with the frame buffer for rendering the blocks to the frame buffer and for transmitting the blocks to the burst data block; and alignment register means interfaced with the block moving means for defining a sub-block and for clipping data rendered to the frame buffer which falls outside the sub-block.
Claim 10
Independent Claim
130 words
A system for transferring blocks directly from a host to a frame buffer comprising: pipeline bypass means interfaced with the host and the frame buffer for bussing data; burst data block means interposed on the pipeline bypass means for receiving data blocks from the host and for transmitting data blocks from the host to the frame buffer; address register means interfaced with the host for receiving block reference addresses and block size data from the host; block moving means interfaced with the frame buffer for rendering the blocks to the frame buffer and for transmitting the blocks to the burst data block; and alignment register means interfaced with the block moving means for defining a sub-block and for clipping data rendered to the frame buffer which falls outside the sub-block.
Claim 11
Dependent Claim
17 words
The system recited in claim 7 wherein the burst data block means is a first-in, first-out register.
Claim 12
Dependent Claim
19 words
The system recited in claim 8 wherein the burst data block means comprises a plurality of first-in, first-out registers.
Claim 13
Dependent Claim
16 words
The system recited in claim 9 wherein the frame buffer is a video random access memory.
Claim 14
Dependent Claim
36 words
The system recited in claim 10 wherein the alignment register means is adapted to receive data from the host indicative of whether the block is addressed relative to a window or relative to the frame buffer.
Claim 15
Dependent Claim
15 words
The system recited in claim 11 wherein the block moving means is an address manipulator.
Claim 16
Independent Claim
167 words
A method of rendering blocks in a graphics system from a host directly to a frame buffer using a burst data block, the system having an address manipulator, pipeline bypass and a pipeline graphics processor, the pipeline graphics processor interfaced with the host and frame buffer and the address manipulator operatively coupled to the host and the frame buffer by the pipeline bypass, comprising the steps of: writing block reference addresses from the host to a data register in the address manipulator via the pipeline bypass; writing block size data from the host to a data register in the address manipulator via the pipeline bypass; writing alignment data from the host to a data register interposed on the pipeline bypass; writing block data from the host to a burst data block; rendering the block data to the reference addresses in the frame buffer; and aligning the block data on the block rendered to the frame buffer, defining a sub-block, and discarding data which falls outside the sub-block.
Claim 17
Independent Claim
167 words
A method of rendering blocks in a graphics system from a host directly to a frame buffer using a burst data block, the system having an address manipulator, pipeline bypass and a pipeline graphics processor, the pipeline graphics processor interfaced with the host and frame buffer and the address manipulator operatively coupled to the host and the frame buffer by the pipeline bypass, comprising the steps of: writing block reference addresses from the host to a data register in the address manipulator via the pipeline bypass; writing block size data from the host to a data register in the address manipulator via the pipeline bypass; writing alignment data from the host to a data register interposed on the pipeline bypass; writing block data from the host to a burst data block; rendering the block data to the reference addresses in the frame buffer; and aligning the block data on the block rendered to the frame buffer, defining a sub-block, and discarding data which falls outside the sub-block.
Claim 18
Dependent Claim
36 words
The method recited in claim 13 wherein the aligning step comprises comparing the block reference addresses with the block size data and discarding data from the block reference addresses which falls outside the block size data.
Claim 19
Dependent Claim
16 words
The method recited in claim 14 wherein the frame buffer is a video random access memory.
Claim 20
Dependent Claim
29 words
The method recited in claim 15 wherein the burst data block comprises a first-in, first-out register for providing independent transfer of data between the host and the frame buffer.
Claim 21
Dependent Claim
23 words
The method recited in claim 16 wherein the block data written to the burst data block from the host corresponds to graphics primitives.
Claim 22
Dependent Claim
16 words
The system recited in claim 17 wherein the rendering step is accomplished with the address manipulator.
Claim 23
Dependent Claim
17 words
The method recited in claim 18 wherein the address manipulator is interfaced directly with the frame buffer.
Claim 24
Dependent Claim
34 words
The method recited in claim 19 wherein the address manipulator is interfaced with a pixel cache buffer for receiving the graphics primitives and the pixel cache buffer is interfaced directly with the frame buffer.
Claim 25
Independent Claim
149 words
A method of transmitting blocks in a graphics system from a host directly to a frame buffer using a burst data block, the system having an address manipulator, pipeline bypass and a pipeline graphics processor, the pipeline graphics processor interfaced with the host and frame buffer and the address manipulator operatively coupled to the host and the frame buffer by the pipeline bypass, comprising the steps of: writing block reference addresses from the host to a data register in the address manipulator via the pipeline bypass; writing block size data from the host to a data register in the address manipulator via the pipeline bypass; writing alignment data from the host to a data register; transmitting block data from the host to the frame buffer; and aligning the block data on the block rendered to the frame buffer, defining a sub-block, and discarding data which falls outside the sub-block.
Claim 26
Independent Claim
149 words
A method of transmitting blocks in a graphics system from a host directly to a frame buffer using a burst data block, the system having an address manipulator, pipeline bypass and a pipeline graphics processor, the pipeline graphics processor interfaced with the host and frame buffer and the address manipulator operatively coupled to the host and the frame buffer by the pipeline bypass, comprising the steps of: writing block reference addresses from the host to a data register in the address manipulator via the pipeline bypass; writing block size data from the host to a data register in the address manipulator via the pipeline bypass; writing alignment data from the host to a data register; transmitting block data from the host to the frame buffer; and aligning the block data on the block rendered to the frame buffer, defining a sub-block, and discarding data which falls outside the sub-block.
References Cited (Backward Citations)
US4958302A
Cited
US5077678A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-08 | 2000-04-08 | 2000-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-08 | 2004-04-08 | 2004-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-08 | 2008-04-08 | 2008-10-08 | $7700.00 | Window Closed / Lapsed |