US5561075A
Expired / Lapsed
US
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Method of manufacturing an active matrix panel
Assignee: Seiko Epson Corp
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Filing: 1995-05-09
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Granted: 1996-10-01
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Expires: 2015-05-09
Abstract
Abstract In the formation and structure of a thin film transistor (TFT), an insulator is formed to cover the surface of the transistor gate electrode, which electrode is separated from an underlying semiconductor layer, having defined source, drain and channel regions, by a gate insulating layer. The overlying gate insulator is formed by anodic oxidation of the gate electrode metal. The formation of the gate insulator thickness and its offset, lateral ΔL, which is defined as the lateral spatial separation between the gate electrode and the source or drain region, can be accurately controlled by the gate electrode anodic oxidation process to provide a reliably and reproducible low OFF current, I OFF , resulting in a TFT that provides for a large I ON /I OFF ratio useful in large area applications wherein electrical charge is required, such as, liquid crystal displays and memory integrated circuits. Preferably, the metal gate electrode is subjected to anodic oxidation at a voltage within the range of between approximately 150 V to 250 V achieving a lateral offset, ΔL, in the range of approximately 100 nm to 200 nm.
Inventors
- 👤 Takashi Nakazawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 11:47
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6715; G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/136; G02F1/1362; G02F1/136286; G02F1/1368; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0321; H10D30/6729; H10D30/6737; H10D30/6739; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01316; Y; Y10; Y10S; Y10S257/00; Y10S257/90
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
228 words
A method of manufacturing an active matrix panel in which data signals are supplied to liquid crystal layers through a plurality of thin film transistors arranged in a matrix of pixels, gate lines and data lines being coupled to each thin film transistor, said method comprising the steps of: forming a semiconductor layer on a substrate; forming a gate insulating film on said semiconductor layer; forming a gate electrode above said gate insulating film and a gate line in electrical contact with said gate electrode; forming a source region and a drain region in said semiconductor layer by adding impurities thereto as donors or acceptors using said gate electrode as a self alignment mask; simultaneously forming an overlying gate insulator on a top and sidewalls of said gate electrode and said gate line by anodic oxidation of said gate electrode and said gate line to reduce the dimensions of said gate electrode and said gate line and simultaneously form a lateral offset, ΔL, from said source region and said drain region to the sidewalls of said gate electrode; and forming a data line in electrical contact with said source region and crossing over said gate line at a cross-over location, wherein said overlying gate insulator is located between said data line and said gate line at said cross-over location to insulate said data line from said gate line.
Claim 2
Independent Claim
228 words
A method of manufacturing an active matrix panel in which data signals are supplied to liquid crystal layers through a plurality of thin film transistors arranged in a matrix of pixels, gate lines and data lines being coupled to each thin film transistor, said method comprising the steps of: forming a semiconductor layer on a substrate; forming a gate insulating film on said semiconductor layer; forming a gate electrode above said gate insulating film and a gate line in electrical contact with said gate electrode; forming a source region and a drain region in said semiconductor layer by adding impurities thereto as donors or acceptors using said gate electrode as a self alignment mask; simultaneously forming an overlying gate insulator on a top and sidewalls of said gate electrode and said gate line by anodic oxidation of said gate electrode and said gate line to reduce the dimensions of said gate electrode and said gate line and simultaneously form a lateral offset, ΔL, from said source region and said drain region to the sidewalls of said gate electrode; and forming a data line in electrical contact with said source region and crossing over said gate line at a cross-over location, wherein said overlying gate insulator is located between said data line and said gate line at said cross-over location to insulate said data line from said gate line.
Claim 3
Dependent Claim
22 words
The method of claim 1 wherein said gate electrode is comprised of tantalum, and wherein said overlying gate insulator comprises tantalum oxide.
Claim 4
Dependent Claim
20 words
The method of claim 1 wherein said gate electrode is selected from the group consisting of tantalum, aluminum and niobium.
Claim 5
Dependent Claim
41 words
The method of claim 1 wherein said gate electrode is subjected to anodic oxidation at a voltage within the range of between 150 V to 250 V, achieving the lateral offset, ΔL, in a range of 100 nm to 200 nm.
Claim 6
Dependent Claim
21 words
The method of claim 1 wherein the gate insulating film is formed by thermally oxidizing a surface of the semiconductor layer.
Claim 7
Dependent Claim
26 words
The method of claim 1 wherein the semiconductor layer is a polysilicon layer formed by decomposing monosilane gas in a temperature of 600° C. using LPCVD.
Claim 8
Dependent Claim
44 words
The method of claim 1 wherein the semiconductor layer is a polysilicon layer formed by first forming an amorphous silicon layer and annealing the amorphous silicon layer at a temperature within a range of 550° C. to 600° C. for 5 to 40 hours.
Claim 9
Dependent Claim
31 words
The method of claim 1 wherein the gate insulating film is formed on a surface of the semiconductor layer by ECR plasma CVD at a temperature of 100° C. or less.
Claim 10
Dependent Claim
28 words
The method of claim 1 wherein the source region and the drain region are formed by implanting phosphorous ions into the semiconductor layer through the gate insulating film.
Claim 11
Dependent Claim
24 words
The method of claim 9 wherein the implanted phosphorous ions are radiated with a laser to reduce the resistance level in the semiconductor layer.
Claim 12
Dependent Claim
27 words
The method as defined in claim 1 wherein the overlying gate insulator is formed having a lateral thickness, ΔI, which is greater than the lateral offset, ΔL.
Claim 13
Dependent Claim
33 words
The method as defined in claim 1 wherein the step of forming the overlying gate insulator by anodic oxidation decreases the width of the gate electrode by about twice the lateral offset, ΔL.
Claim 14
Independent Claim
273 words
A method of manufacturing an active matrix panel in which data signals are supplied to liquid crystal layers through a plurality of thin film transistors arranged in a matrix of pixels, gate lines and data lines being coupled to each thin film transistor, said method comprising the steps of: forming a first silicon thin film region and a second silicon thin film region on a surface of a substrate; forming a semiconductor layer on the surface of the substrate between said first and second thin film regions; forming a gate insulating film on a surface of said semiconductor layer; forming a gate electrode above said gate insulating film and a gate line in electrical contact with said gate electrode; implanting ions into said first and second thin film regions and said semiconductor layer through said gate insulating film using said gate electrode as a self-alignment mask to form a source region and a drain region; simultaneously subjecting a surface of said gate electrode and said gate line to anodic oxidation to reduce the dimensions of said gate electrode and said gate line to form an overlying gate insulator on a top and sidewalls of said gate electrode and said gate line which simultaneously forms a lateral offset, ΔL, from said source region and said drain region to the sidewalls of said gate electrode; and forming a data line in electrical contact with said source region and crossing over said gate line at a cross-over location, wherein said overlying gate insulator is located between said data line and said gate line at said cross-over location to insulate said data line from said gate line.
Claim 15
Independent Claim
273 words
A method of manufacturing an active matrix panel in which data signals are supplied to liquid crystal layers through a plurality of thin film transistors arranged in a matrix of pixels, gate lines and data lines being coupled to each thin film transistor, said method comprising the steps of: forming a first silicon thin film region and a second silicon thin film region on a surface of a substrate; forming a semiconductor layer on the surface of the substrate between said first and second thin film regions; forming a gate insulating film on a surface of said semiconductor layer; forming a gate electrode above said gate insulating film and a gate line in electrical contact with said gate electrode; implanting ions into said first and second thin film regions and said semiconductor layer through said gate insulating film using said gate electrode as a self-alignment mask to form a source region and a drain region; simultaneously subjecting a surface of said gate electrode and said gate line to anodic oxidation to reduce the dimensions of said gate electrode and said gate line to form an overlying gate insulator on a top and sidewalls of said gate electrode and said gate line which simultaneously forms a lateral offset, ΔL, from said source region and said drain region to the sidewalls of said gate electrode; and forming a data line in electrical contact with said source region and crossing over said gate line at a cross-over location, wherein said overlying gate insulator is located between said data line and said gate line at said cross-over location to insulate said data line from said gate line.
Claim 16
Dependent Claim
20 words
The method of claim 13 wherein the gate electrode is selected from the group consisting of tantalum, aluminum and niobium.
Claim 17
Dependent Claim
21 words
The method of claim 13 wherein the gate insulating film is formed by thermally oxidizing the surface of the semiconductor layer.
Claim 18
Dependent Claim
30 words
The method of claim 13 wherein the semiconductor layer is a polysilicon layer formed by first forming an amorphous silicon layer and irradiating the amorphous silicon layer with a laser.
Claim 19
Dependent Claim
27 words
The method as defined in claim 13 wherein the overlying gate insulator is formed having a lateral thickness, ΔI, which is greater than the lateral offset, ΔL.
Claim 20
Dependent Claim
33 words
The method as defined in claim 13 wherein the step of forming the overlying gate insulator by anodic oxidation decreases the width of the gate electrode by about twice the lateral offset, ΔL.
Claim 21
Dependent Claim
36 words
The method of claim 13 further comprising the step of forming a first insulating film on a surface of the gate insulating film with said gate electrode formed on a surface of the first insulating film.
References Cited (Backward Citations)
JPS5524420A
Cited
JPS5787175A
Cited
US4469568A
Cited
JPS58115864A
Cited
US5474942A
Cited
US4727044A
Cited
JPS61147574A
Cited
JPS61156885A
Cited
JPS61185724A
Cited
JPS61252667A
Cited
JPS61105873A
Cited
JPS63178560A
Cited
JPH01185522A
Cited
JPH01183853A
Cited
JPH0285826A
Cited
JPH0290683A
Cited
JPH02148831A
Cited
JPH02306664A
Cited
JPH02307273A
Cited
JPH03108319A
Cited
US5165075A
Cited
US5289030A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1999-10-01 | 2000-04-01 | 2000-10-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-01 | 2004-04-01 | 2004-10-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-01 | 2008-04-01 | 2008-10-01 | $7700.00 | Window Closed / Lapsed |