Abstract An apparatus and method for controlling the stopping of the clock signal utilized by the processing unit of a computer system comprises the use of a novel external pin which can be enabled to initiate a sequence of events that results in the halting of the internal clock signal. The invention includes a microcode engine that responds to the assertion of the external pin by executing a sequence of steps which stops the current instruction on an instruction boundary. A logic circuit then generates a signal that masks the clock signal produced by the system's phase-locked loop. An interrupt mechanism is also utilized to prioritize the occurrence of the external signal among other system interrupts. The interrupt mechanism insures that the processor never has its clock stopped in the middle of a bus cycle.
A method of testing a microprocessor comprising the steps of: (a) providing a reference oscillatory signal to said microprocessor, said microprocessor generating an internal clock signal therefrom; (b) asserting an external pin of said microprocessor to initiate the routine first placing said microprocessor in a known state and then asserting a logic signal which masks said internal clock signal from at least a portion of said microprocessor; (c) retrieving information associated with said known state from said microprocessor.
Claim 2
Independent Claim
78 words
A method of testing a microprocessor comprising the steps of: (a) providing a reference oscillatory signal to said microprocessor, said microprocessor generating an internal clock signal therefrom; (b) asserting an external pin of said microprocessor to initiate the routine first placing said microprocessor in a known state and then asserting a logic signal which masks said internal clock signal from at least a portion of said microprocessor; (c) retrieving information associated with said known state from said microprocessor.
Claim 3
Dependent Claim
30 words
The method of claim 1 further comprising the step of: (d) deasserting said external pin to recouple said internal clock signal to said at least a portion of said microprocessor.
Claim 4
Dependent Claim
24 words
The method of claim 2 further comprising the step (e) resuming bus activity associated with said microprocessor following the deassertion of said external pin.
Claim 5
Dependent Claim
25 words
The method of claim 1 wherein said routine further comprises issuing a special bus cycle just prior to deactivating a bus unit of said microprocessor.
Claim 6
Independent Claim
20 words
The method of claims 1, 2, 3, or 4 wherein said reference oscillatory signal is provided continuously to said microprocessor.