US5559970A
Expired / Lapsed
US
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Crossbar switch for multi-processor, multi-memory system for resolving port and bank contention through the use of aligners, routers, and serializers
Assignee: NEC Corp
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Filing: 1994-05-04
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Granted: 1996-09-24
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Expires: 2014-05-04
Abstract
Abstract A self-routing crossbar switch interconnects a plurality of processors with a plurality of memory modules. In a self-routing crossbar switch connecting N processors and N memory modules, a processor is connected to each input port and a memory module is connected to each output port; each of the N processors can transmit a memory request simultaneously provided that there is no port contention and no bank contention. Port contention occurs if two or more processors attempt to access the same output port of the self-routing crossbar switch at the same time. The memory module consists of several memory banks that are connected in an interleaved manner. If the memory bank is accessed before it is ready to accept a new request, bank contention is said to have occurred. In the self-routing crossbar switch the requests directed to a port are first passed through an aligner and a conflict resolution logic. There is one aligner associated with each output port. The aligner inputs the requests directed at an output port and aligns them so that, at the output of the aligner, all the active requests appear in a consecutive fashion. The conflict resolution logic resolves the port and bank contention.
Inventors
- 👤 Vinod Sharma
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 02:52
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/0428; H04Q11/0478; G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/173; G06F15/17356; G06F15/17368; G06F15/17375; H04L; H04L49/00; H04L49/25; H04L49/253; H04L49/10; H04L49/101; H04L49/30; H04L49/3018; H04L49/40
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
232 words
A crossbar switch in a multi-processing system, having N input ports respectively connected to N processors, wherein N is an integer, and N output ports respectively connected to N memory modules, comprising: decoders respectively coupled to said input ports for distributing memory access requests from said processors to output ports among said N output ports which are designated as destination ports by said memory access requests; N×N first-in first-out buffers provided at respective outputs of said decoders and separated into N groups, each of said N groups containing N buffers connected to a common destination port; N N-input and N-output aligners, coupled to outputs of said respective groups of N×N first-in first-out buffers, for aligning effective memory access requests in series; and N serializers connected to outputs of said respective aligners, for serializing the memory access requests aligned by said aligners and outputting to one of said output ports, wherein each of said N-input and N-output aligners includes, two (N/2)-input and (N/2)-output aligners, having two N/2 inputs, each of which correspond to a respective input of said N-input and N-output aligner, for aligning effective memory access requests in series; and an N-input and N-output router, having N inputs, each of which correspond to a respective output of said two (N/2)-input and (N/2)-output aligners, for shifting forward the memory access requests in order so that said memory access requests are packed in series.
Claim 2
Dependent Claim
232 words
A crossbar switch in a multi-processing system, having N input ports respectively connected to N processors, wherein N is an integer, and N output ports respectively connected to N memory modules, comprising: decoders respectively coupled to said input ports for distributing memory access requests from said processors to output ports among said N output ports which are designated as destination ports by said memory access requests; N×N first-in first-out buffers provided at respective outputs of said decoders and separated into N groups, each of said N groups containing N buffers connected to a common destination port; N N-input and N-output aligners, coupled to outputs of said respective groups of N×N first-in first-out buffers, for aligning effective memory access requests in series; and N serializers connected to outputs of said respective aligners, for serializing the memory access requests aligned by said aligners and outputting to one of said output ports, wherein each of said N-input and N-output aligners includes, two (N/2)-input and (N/2)-output aligners, having two N/2 inputs, each of which correspond to a respective input of said N-input and N-output aligner, for aligning effective memory access requests in series; and an N-input and N-output router, having N inputs, each of which correspond to a respective output of said two (N/2)-input and (N/2)-output aligners, for shifting forward the memory access requests in order so that said memory access requests are packed in series.
Claim 3
Dependent Claim
110 words
The crossbar switch as set forth in claim 1, wherein each of said N-input and N-output aligners recursively comprises: said two (N/2)-input and (N/2)-output aligners, having two N/2 inputs, each of which correspond to a respective input of said N-input and N-output aligner, for aligning effective memory access requests in series; and an N-input and N-inputs router, having N outputs, each of which correspond to an output of said two (N/2)-input and (N/2)-output aligners, for shifting forward the memory access requests in order so that said memory access requests are packed in series, wherein a 2-input and 2-output aligner and a 4-input and 4-output router are provided at a minimum.
Claim 4
Dependent Claim
83 words
The crossbar switch as set forth in claim 1, wherein said N-input and N-output router processes memory access requests consecutively from 0 to N/2-1, such that, if an i-th memory access request is effective, the i-th memory access request is output at an i-th output of said N-input and N-output router, but if the i-th memory access request is not effective, the (N/2)th to (N-1)th memory access requests are output respectively at the i-th to (i+N/2-1)th outputs of said N-input and N-output router.
Claim 5
Dependent Claim
51 words
The crossbar switch as set forth in claim 1, wherein each of said serializers includes a N-stage shift register taking the outputs of said respective N-input and N-output aligner as inputs for respective stages of said shift register, and the outputs from said shift register are output to said output ports.
Claim 6
Dependent Claim
64 words
The crossbar switch as set forth in claim 4, wherein each of said serializers includes a counting means for counting memory cycles for each memory bank which is contained in said memory modules, to maintain said shift register in a hold condition until a predetermined number of memory cycles has been counted by said counting means corresponding to the memory bank to be accessed.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-09-24 | 2000-03-25 | 2000-09-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-09-24 | 2004-03-25 | 2004-09-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-09-24 | 2008-03-25 | 2008-09-24 | $7700.00 | Window Closed / Lapsed |