Method for isolating non-volatile memory cells

Claim 1

A method of fabricating semiconductor integrated circuit non-volatile memory cells having memory cell isolation comprising the steps of: defining active regions of said memory cells on a semiconductor substrate of a first conductivity type by forming a masking layer, said masking layer leaving exposed regions of the semiconductor substrate; implanting impurities of the first conductivity type into said semiconductor substrate to form lightly-doped regions of the first conductivity type in the regions exposed by said masking layer; utilizing said masking layer as shielding for an oxidation procedure of said semiconductor substrate to form field oxide layers of said memory cells on top of said lightly-doped regions of the first conductivity type; removing said masking layer; forming an oxide layer on top of said active regions of said memory cells; forming floating gate strip layers for said memory cells each on top of one of said field oxide layers and said oxide layer, wherein said floating gate strip layers are divided by isolating trenches and aligned on top of said oxide layers with edges extending outwardly to cover a portion of the width of said field oxide layers; implanting impurities of the first conductivity type through said isolating trenches between said floating gate strip layers to form heavily-doped regions of the first conductivity type in said semiconductor substrate, said heavily-doped regions being formed within said lightly-doped regions located underneath said field oxide layers; forming subsequently on top of said substrate a gate dielectric layer and word line polysilicon layer and implementing an etching procedure against said gate dielectric and word line polysilicon layers to form independent word lines and isolated floating gate layers, said floating gate layers being covered by said word lines; and implanting impurities of a second conductivity type into said active regions utilizing said word lines and field oxide layers as masks to form drains and sources for said memory cells.

Claim 2

A method of fabricating semiconductor integrated circuit non-volatile memory cells having memory cell isolation comprising the steps of: defining active regions of said memory cells on a semiconductor substrate of a first conductivity type by forming a masking layer, said masking layer leaving exposed regions of the semiconductor substrate; implanting impurities of the first conductivity type into said semiconductor substrate to form lightly-doped regions of the first conductivity type in the regions exposed by said masking layer; utilizing said masking layer as shielding for an oxidation procedure of said semiconductor substrate to form field oxide layers of said memory cells on top of said lightly-doped regions of the first conductivity type; removing said masking layer; forming an oxide layer on top of said active regions of said memory cells; forming floating gate strip layers for said memory cells each on top of one of said field oxide layers and said oxide layer, wherein said floating gate strip layers are divided by isolating trenches and aligned on top of said oxide layers with edges extending outwardly to cover a portion of the width of said field oxide layers; implanting impurities of the first conductivity type through said isolating trenches between said floating gate strip layers to form heavily-doped regions of the first conductivity type in said semiconductor substrate, said heavily-doped regions being formed within said lightly-doped regions located underneath said field oxide layers; forming subsequently on top of said substrate a gate dielectric layer and word line polysilicon layer and implementing an etching procedure against said gate dielectric and word line polysilicon layers to form independent word lines and isolated floating gate layers, said floating gate layers being covered by said word lines; and implanting impurities of a second conductivity type into said active regions utilizing said word lines and field oxide layers as masks to form drains and sources for said memory cells.

Claim 5

The method of fabricating semiconductor integrated circuit non-volatile memory devices having memory cell isolation according to claims 1, wherein said masking layer comprises an oxide and nitride layer.