Method and apparatus for transferring data between a master unit and a plurality of slave units

Claim 2

A data transferring apparatus, comprising a master unit; and a plurality of slave units, for transferring data between the master unit (MU) and said plurality of slave units (SU0, SU1, SU2, SU3) according to a synchronizing signal (CLK) supplied to each unit, each of said master unit (MU) and plurality of slave units (SU0, SU1, SU2, SU3) being connected with each other, said master unit comprising: a plurality of storing circuits (FF1, FF2, FF3, FF4) which respectively store transmission request signals representing transmission requests from respective slave units (SU0, SU1, SU2, SU3); a transmission allowance signal generating circuit (13), connected to the plurality of storing circuits, for generating a transmission allowance signal representing the transmission allowance of only one slave unit (SU0, SU1, SU2, or SU3) according to output signals received from the plurality of storing circuits indicating stored contents of said plurality of storing circuits (FF1, FF2, FF3, FF4) and a predetermined priority order; transmission request rewriting circuits (51, 52, 53, 54) each coupled to a respective storing circuit, for rewriting the stored contents of a respective storing circuit (FF1, FF2, FF3 or FF4) which stores the transmission request signal from the respective slave unit (SU0, SU1, SU2 or SU3), which has been allowed to transmit data based upon a signal from said transmission allowance signal generating circuit (13), into a state where there is no transmission request; a detecting circuit (50), coupled to said storing circuits, for detecting a predetermined state where there is no transmission request obtained by rewriting all of the stored contents of said plurality of storing circuit (FF1, FF2, FF3, FF4); selecting circuits (SEL1, SEL2, SEL3, SEL4) each being respectively connected to a respective one of the plurality of storing circuits and also to a respective one of the transmission request rewriting circuits, for selecting either a rewriting operation performed by a respective transmission request rewriting circuit (51, 52, 53, 54), or a signal input operation causing the transmission request signals from the respective slave units (SU0, SU1, SU2, SU3) to be stored in respective storing circuits (FF1, FF2, FF3, FF4); and a control circuit (NAND 1) having an output connected to each of said selecting circuits (SEL1, SEL2, SEL3, SEL4) and an input connected to receive an input signal from said detecting circuit for transmitting a signal to select either said signal input operation only when said predetermined state is detected by said detecting circuit or said rewriting operation when said predetermined state is not detected by said detecting circuit.

Claim 3

A data transferring apparatus as set forth in claim 1, wherein only one of said transmission request rewriting circuits (51, 52, 53 or 54), which corresponds to a slave unit 53 or 54), which corresponds to a slave unit having the most significant priority order among the plurality of slave units (SU0, SU1, SU2, SU3) having a transmission request, rewrites the stored contents of a storing circuit (FF1, FF2, FF3 or FF4) corresponding thereto.

Claim 4

A data transferring apparatus as set forth in claim 1, wherein said plurality of storing circuits (FF1, FF2, FF3, FF4) each include flip flops, which output predetermined signals when a transmission request from a slave respective unit (SU0, SU1, SU2, SU3) corresponding thereto is stored therein.

Claim 5

A data transferring apparatus, comprising a master unit; and a plurality of slave units, for transferring data between the master unit (MU) and said plurality of slave units (SU0, SU1, SU2, SU3) according to a synchronizing signal (CLK) supplied to each unit, each of said master unit (MU) and plurality of slave units (SU0, SU1, SU2, SU3) being connected with each other, said master unit comprising: a plurality of storing circuits (FF1, FF2, FF3, FF4) which respectively store transmission request signals representing transmission requests from respective slave units (SU0, SU1, SU2, SU3); a transmission allowance signal generating circuit (13), connected to the plurality of storing circuits, for generating a transmission allowance signal representing the transmission allowance of only one slave unit (SU0, SU1, SU2, or SU3) according to output signals received from the plurality of storing circuits indicating stored contents of said plurality of storing circuits (FF1, FF2, FF3, FF4) and a predetermined priority order; transmission request rewriting circuits (51, 52, 53, 54) each coupled to a respective storing circuit, for rewriting the stored contents of a respective storing circuit (FF1, FF2, FF3 or FF4) which stores the transmission request signal from the respective slave unit (SU0, SU1, SU2 or SU3), which has been allowed to transmit data based upon a signal from said transmission allowance signal generating circuit (13), into a state where there is no transmission request; a detecting circuit (50), coupled to said storing circuits, for detecting a predetermined state where there is no transmission request obtained by rewriting all of the stored contents of said plurality of storing circuits (FF1, FF2, FF3, FF4); selecting circuits (SEL1, SEL2, SEL3, SEL4) each being respectively connected to a respective one of the plurality of storing circuits and also to a respective one of the transmission request rewriting circuits, for selecting either a rewriting operation performed by a respective transmission request rewriting circuit (51, 52, 53, 54), or a signal input operation causing the transmission request signals from the respective slave units (SU0, SU1, SU2, SU3) to be stored in respective storing circuits (FF1, FF2, FF3, FF4); and a control circuit (NAND 1) having an output connected to each of said selecting circuits (SEL1, SEL2, SEL3, SEL4) and an input connected to receive an input signal from said detecting circuit for transmitting a signal to select either said signal input operation only when said predetermined state is detected by said detecting circuit or said rewriting operation when said predetermined state is not detected by said detecting circuit, wherein said detecting circuit (50) comprises an AND gate (AND5) receiving all outputs of said plurality of storing circuits (FF1, FF2, FF3, FF4) as inputs thereof; and a flip-flop (FF5), coupled to said AND gate, for storing and outputting the outputs of said AND gate (AND5).

Claim 6

A data transferring apparatus, comprising a master unit; and a plurality of slave units, for transferring data between the master unit (MU) and said plurality of slave units (SU0, SU1, SU2, SU3) according to a synchronizing signal (CLK) supplied to each unit, each of said master unit (MU) and plurality of slave units (SU0, SU1, SU2, SU3) being connected with each other, said master unit comprising: a plurality of storing circuits (FF1, FF2, FF3, FF4) which respectively store transmission request signals representing transmission requests from respective slave units (SU0, SU1, SU2, SU3); a transmission allowance signal generating circuit (13), connected to the plurality of storing circuits, for generating a transmission allowance signal representing the transmission allowance of only one slave unit (SU0, SU1, SU2, or SU3) according to output signals received from the plurality of storing circuits indicating stored contents of said plurality of storing circuits (FF1, FF2, FF3, FF4) and a predetermined priority order; transmission request rewriting circuits (51, 52, 53, 54) each coupled to a respective storing circuit, for rewriting the stored contents of a respective storing circuit (FF1, FF2, FF3 or FF4) which stores the transmission request signal from the respective slave unit (SU0, SU1, SU2 or SU3), which has been allowed to transmit data based upon a signal from said transmission allowance signal generating circuit (13), into a state where there is no transmission request; a detecting circuit (50), coupled to said storing circuits, for detecting a predetermined state where there is no transmission request obtained by rewriting all of the stored contents of said plurality of storing circuits (FF1, FF2, FF3, FF4); selecting circuits (SEL1, SEL2, SEL3, SEL4) each being respectively connected to a respective one of the plurality of storing circuits and also to a respective one of the transmission request rewriting circuits, for selecting either a rewriting operation performed by a respective transmission request rewriting circuit (51, 52, 53, 54), or a signal input operation causing the transmission request signals from the respective slave units (SU0, SU1, SU2, SU3) to be stored in respective storing circuits (FF1, FF2, FF3, FF4); and a control circuit (NAND 1) having an output connected to each of said selecting circuits (SEL1, SEL2, SEL3, SEL4) and an input connected to receive an input signal from said detecting circuit for transmitting a signal to select either said signal input operation only when said predetermined state is detected by said detecting circuit or said rewriting operation when said predetermined state is not detected by said detecting circuit, wherein said detecting circuit (50) comprises an AND gate (AND5) receiving all outputs of said plurality of storing circuits (FF1, FF2, FF3, FF4) as inputs thereof; and a flip-flop (FF5), coupled to said AND gate, for storing and outputting the outputs of said AND gate (AND5).

Claim 7

A data transferring apparatus as set forth in claim 4, wherein said control circuit (NAND1) controls said selecting circuits (SEL1, SEL2, SEL3, SEL4) according to a signal (LP) supplied thereto at a predetermined timing and an output (S1) of said flip-flop (FF5).