Method for implementing time switching and a time switch

Claim 3

A method according to claim 1, comprising: forming the read address relating to a respective said memory location by adding a respective said relative read address to a respective said write address from which a fixed delay is subtracted.

Claim 4

A method according to claim 2, comprising: forcing a relative read address to become zero during time slots which are not cross-connected.

Claim 5

A time switch for implementing time switching in a synchronous digital hierarchy (SDH) network, in which the contents of time slots of an incoming STM-1 signal are written into a memory at memory locations determined by a write address, and read from said memory at memory locations indicated by switching data contained in an address control memory, for switching the contents of any time slot in the frame structure of an incoming STM-1 signal, to any time slot in the outgoing frame structure of an STM-1 signal, said time switch comprising: a memory arranged to have written thereinto at respective addresses the contents of a succession of incoming time slots; first means controlling writing into said memory and providing an indication of respective write addresses; second means controlling reading from said memory, said second means comprising: an address control memory, switching data of which, provided as an output thereof, indicates memory addresses of said memory from which data is to be read; an adder circuit having connected as inputs thereto: said indication of respective write addresses, from which a fixed delay has been subtracted, and said output of said address control memory, in the form of an address, which, in frame blocks starting from columns 19, 82, 145 and 208 of a respective STM-1 frame give switching data of each time slot of the frame block as a relative address consisting of the location difference, within the respective frame block, between an outgoing time slot and an incoming time slot to be switched thereto, said relative address having a permitted value range of 63 address values within each column of a respective said frame block; and means for forcing the output of the address control memory to zero during columns 1 to 12 of the respective STM-1 frame.

Claim 6

A time switch for implementing time switching in a synchronous digital hierarchy (SDH) network, in which the contents of time slots of an incoming STM-1 signal are written into a memory at memory locations determined by a write address, and read from said memory at memory locations indicated by switching data contained in an address control memory, for switching the contents of any time slot in the frame structure of an incoming STM-1 signal, to any time slot in the outgoing frame structure of an STM-1 signal, said time switch comprising: a memory arranged to have written thereinto at respective addresses the contents of a succession of incoming time slots; first means controlling writing into said memory and providing an indication of respective write addresses; second means controlling reading from said memory, said second means comprising: an address control memory, switching data of which, provided as an output thereof, indicates memory addresses of said memory from which data is to be read; an adder circuit having connected as inputs thereto: said indication of respective write addresses, from which a fixed delay has been subtracted, and said output of said address control memory, in the form of an address, which, in frame blocks starting from columns 19, 82, 145 and 208 of a respective STM-1 frame give switching data of each time slot of the frame block as a relative address consisting of the location difference, within the respective frame block, between an outgoing time slot and an incoming time slot to be switched thereto, said relative address having a permitted value range of 63 address values within each column of a respective said frame block; and means for forcing the output of the address control memory to zero during columns 1 to 12 of the respective STM-1 frame.