Method of making a semiconductor memory device having an increased capacitance of memory cell

Claim 1

A method for fabricating a semiconductor memory device having a memory cell transistor and a memory cell capacitor, said method comprising the steps of: forming the memory cell transistor on a substrate; covering the memory cell transistor by an insulator layer; providing a contact hole through the insulator layer to expose a part of the memory cell transistor; depositing a first conductor material layer on the insulator layer such that the first conductor material layer establishes a contact to the exposed part of the memory cell transistor; depositing a photoresist layer on the first conductor material layer; exposing the photoresist layer to an optical beam via a mask that carries a plurality of primary patterns each corresponding generally to the pattern of the memory cell capacitor to be formed, said mask further having a plurality of secondary patterns to surround each of the primary patterns, each of said secondary patterns comprising a plurality of projections separated from each other and projecting outward from each of the primary patterns; patterning the photoresist layer exposed by the optical beam; patterning the first conductor material layer using the patterned photoresist layer as a mask to form a first electrode of the memory cell capacitor, the first electrode having an upper major surface, of a nominally rectangular configuration and corresponding, nominally rectangular periphery, and a lateral wall substantially perpendicular to the upper major surface of the substrate, the lateral wall defining the actual periphery of the first electrode and, when viewed in a direction perpendicular to the upper major surface of the substrate, the lateral wall having an undulating form defined by a smooth curve extending outwardly and inwardly of the nominally rectangular periphery along the full extent thereof; depositing a dielectric film on said first conductor material layer to cover a top surface and a side wall of the first electrode; and depositing a second conductive material layer on said dielectric film to cover a top surface and a side wall of the dielectric film respectively corresponding to the top surface and the side wall of the first electrode.

Claim 2

A method for fabricating a semiconductor memory device having a memory cell transistor and a memory cell capacitor, said method comprising the steps of: forming the memory cell transistor on a substrate; covering the memory cell transistor by an insulator layer; providing a contact hole through the insulator layer to expose a part of the memory cell transistor; depositing a first conductor material layer on the insulator layer such that the first conductor material layer establishes a contact to the exposed part of the memory cell transistor; depositing a photoresist layer on the first conductor material layer; exposing the photoresist layer to an optical beam via a mask that carries a plurality of primary patterns each corresponding generally to the pattern of the memory cell capacitor to be formed, said mask further having a plurality of secondary patterns to surround each of the primary patterns, each of said secondary patterns comprising a plurality of projections separated from each other and projecting outward from each of the primary patterns; patterning the photoresist layer exposed by the optical beam; patterning the first conductor material layer using the patterned photoresist layer as a mask to form a first electrode of the memory cell capacitor, the first electrode having an upper major surface, of a nominally rectangular configuration and corresponding, nominally rectangular periphery, and a lateral wall substantially perpendicular to the upper major surface of the substrate, the lateral wall defining the actual periphery of the first electrode and, when viewed in a direction perpendicular to the upper major surface of the substrate, the lateral wall having an undulating form defined by a smooth curve extending outwardly and inwardly of the nominally rectangular periphery along the full extent thereof; depositing a dielectric film on said first conductor material layer to cover a top surface and a side wall of the first electrode; and depositing a second conductive material layer on said dielectric film to cover a top surface and a side wall of the dielectric film respectively corresponding to the top surface and the side wall of the first electrode.