Demodulation logic unit adaptable to multiple data protocols

Claim 2

A data demodulation logic unit adaptable to multiple data modulation protocols for decoding data, comprising in combination: an arithmetic logic unit including an input, a plurality of registers and an output controllably operable to convert a base band signal, coupled to said input, to a demodulated data signal representing an estimate of decoded data at said output, a state machine embodied in electronic hardware, coupled to said arithmetic logic unit, said state machine operating in a mode to control said arithmetic logic unit and to select one or more of said plurality of registers for outputting to the output, said mode selectively corresponding to a data modulation protocol and an error correcting circuit coupled to the arithmetic logic unit for receiving the estimate of the decoded data from at least the one or more selected registers.

Claim 3

The data demodulation logic unit of claim 1 wherein said arithmetic logic unit further includes an adder subtractor.

Claim 4

The data demodulation logic unit of claim 2 wherein said arithmetic logic unit further includes a first plurality of registers.

Claim 5

The data demodulation logic unit of claim 3 wherein said arithmetic logic unit further includes a second plurality of registers.

Claim 6

The data demodulation logic unit of claim 4 wherein said arithmetic logic unit further includes a shift register selectively coupled to said second plurality of registers.

Claim 7

The data demodulation logic unit of claim 5 wherein said state machine is embodied in an integrated circuit.

Claim 8

The data demodulation logic unit of claim 1 wherein said state machine and said arithmetic logic unit are embodied in an integrated circuit.

Claim 9

A data receiver having the capability of receiving multiple data protocols, comprising in combination: a receiver arranged to receive a radio frequency signal modulated by data and provide a base band signal, an arithmetic logic unit including an input coupled to said base band signal,a plurality of registers and an output, said arithmetic logic unit controllably operable to convert said base band signal to a demodulated data signal representing an estimate of decoded data, a state machine embodied in electronic hardware, coupled to said arithmetic logic unit, said state machine operating in a mode to control said arithmetic logic unit and to select one or more of said plurality of registers for outputting to the output, said mode selectively corresponding to one of said multiple data protocols and an error correcting circuit coupled to the arithmetic logic unit for receiving the estimate of the decoded data from at least the one or more selected registers.

Claim 10

A data receiver having the capability of receiving multiple data protocols, comprising in combination: a receiver arranged to receive a radio frequency signal modulated by data and provide a base band signal, an arithmetic logic unit including an input coupled to said base band signal,a plurality of registers and an output, said arithmetic logic unit controllably operable to convert said base band signal to a demodulated data signal representing an estimate of decoded data, a state machine embodied in electronic hardware, coupled to said arithmetic logic unit, said state machine operating in a mode to control said arithmetic logic unit and to select one or more of said plurality of registers for outputting to the output, said mode selectively corresponding to one of said multiple data protocols and an error correcting circuit coupled to the arithmetic logic unit for receiving the estimate of the decoded data from at least the one or more selected registers.

Claim 11

The data receiver of claim 8 wherein said arithmetic logic unit further includes an adder subtractor.

Claim 12

The data receiver of claim 9 wherein said arithmetic logic unit further includes a first plurality of registers.

Claim 13

The data receiver of claim 10 wherein said arithmetic logic unit further includes a second plurality of registers.

Claim 14

The data receiver of claim 11 wherein said arithmetic logic unit further includes a shift register selectively coupled to said second plurality of registers.

Claim 15

The data receiver of claim 12 wherein said state machine is embodied in an integrated circuit.

Claim 16

The data receiver of claim 8 wherein said state machine and said arithmetic logic unit are embodied in an integrated circuit.

Claim 17

The data receiver of claim 14 wherein said mode corresponds to a radio data link access procedure protocol.

Claim 18

A data demodulation logic unit adaptable to multiple data modulation protocols, comprising in combination: an adder subtractor, having a first input, a second input, an output, and a control input, for providing an output signal at said output, said output signal representing the result of said adder subtractor adding or subtracting a first signal at said first input and a second signal at said second input; a first plurality of registers, each having an input, an output, and a control input, said plurality of registers arranged such that the contents of a register can be selectively applied to said first input, a second plurality of registers, each having an input with at least one input coupled to a base band signal, an output, and a control input, said second plurality of registers arranged such that the contents of a register can be selectively applied to said second input, a state machine embodied in electronic hardware, coupled to each said control input of both said first plurality of registers and said second plurality of registers, and coupled to said control input of said adder subtractor, said state machine selectively operable in a plurality of demodulator modes, each demodulator mode corresponding to a data modulation protocol.

Claim 19

A data demodulation logic unit adaptable to multiple data modulation protocols, comprising in combination: an adder subtractor, having a first input, a second input, an output, and a control input, for providing an output signal at said output, said output signal representing the result of said adder subtractor adding or subtracting a first signal at said first input and a second signal at said second input; a first plurality of registers, each having an input, an output, and a control input, said plurality of registers arranged such that the contents of a register can be selectively applied to said first input, a second plurality of registers, each having an input with at least one input coupled to a base band signal, an output, and a control input, said second plurality of registers arranged such that the contents of a register can be selectively applied to said second input, a state machine embodied in electronic hardware, coupled to each said control input of both said first plurality of registers and said second plurality of registers, and coupled to said control input of said adder subtractor, said state machine selectively operable in a plurality of demodulator modes, each demodulator mode corresponding to a data modulation protocol.