Headend processing for a digital transmission system

Claim 2

A headend apparatus comprising: a first input for receiving plurality first digital time division multiplexed channels of program information from a first program source; a second input for receiving one or more second digital channels of program information from a second program source; a demultiplexing circuit coupled to said first input for demultiplexing the first channel of digital time division multiplexed program information into a plurality of demultiplexed digital channels of program information; a switching circuit to which the plurality of demultiplexed digital channels and the and second digital channels of programs information are applied; and a switch control for controlling said switching circuit to output third channels of program information comprising combinations of programs information of the first and second channels for distribution to subscriber.

Claim 3

The headend apparatus according to claim 1 wherein said first program source comprise a remote program source.

Claim 4

The headend apparatus according to claim 1 wherein: said switching circuit comprises a crosspoint switch.

Claim 5

The headend apparatus according to claim 1 wherein said second input receives second channels of interleaved digital program information.

Claim 6

The headend apparatus according to claim 4 wherein the demultiplexing circuit receives the time division multiplexed digital program information from the first channel and outputs demultiplexed program information to said switching circuit.

Claim 7

The headend apparatus according to claim 5 further comprising a circuit coupled to the to the output of said switching circuit for combining the program information from the switching circuit for distribution to a subscriber.

Claim 8

The headend apparatus according to claim 1 wherein said switch control comprises a microprocessor.

Claim 9

The headend apparatus according to claim 1 further comprising: a non-volatile memory coupled to said switch control for storing a configuration of said switching circuit as determined by said switch control.

Claim 10

The headend apparatus according to claim 1 wherein the program information of the first and second channels includes digital audio information.

Claim 11

A headend apparatus comprising: inputs for receiving first channel of time division multiplexed program information and second channel of program information from first and second program sources; inputs for receiving first and second control information from first and second control source; a demultiplexer circuit for demultiplexing the first channel of time division multiplexed program information into a plurality of demultiplexer channels of program information; a switching circuit to which said first demultiplexed channel and second channel of program information is applied; a switch control for controlling said switching circuit to output channels of program information comprising combinations of the first demultiplexed channel and second channel of program information for output to a subscriber; and means for selectively providing the received first and second control information to the channels output from said switching circuit.

Claim 12

A headend apparatus comprising: inputs for receiving first channel of time division multiplexed program information and second channel of program information from first and second program sources; inputs for receiving first and second control information from first and second control source; a demultiplexer circuit for demultiplexing the first channel of time division multiplexed program information into a plurality of demultiplexer channels of program information; a switching circuit to which said first demultiplexed channel and second channel of program information is applied; a switch control for controlling said switching circuit to output channels of program information comprising combinations of the first demultiplexed channel and second channel of program information for output to a subscriber; and means for selectively providing the received first and second control information to the channels output from said switching circuit.

Claim 13

The headend apparatus according to claim 10 wherein said switching circuit comprises a crosspoint switch.

Claim 14

The headend apparatus according to claim 10 wherein said inputs include an input receiving first program and first control information from a remote program and control source.

Claim 17

A headed apparatus comprising: inputs for receiving first and second program information from one or more program sources; inputs for receiving first and second subscriber control information from first and second control sources; a switching circuit to which said first and second program information is applied; a switch control for controlling said switching circuit to output a channel of program information comprising combinations of the first and second programs information for output to a subscriber; means for selectively providing either the first or the second subscriber control information to the output channel from said switching circuit; and a scrambler coupled to said switching circuit for scrambling the subscriber control information and program information output from said switching circuit to the subscriber.

Claim 18

A headed apparatus comprising: inputs for receiving first and second program information from one or more program sources; inputs for receiving first and second subscriber control information from first and second control sources; a switching circuit to which said first and second program information is applied; a switch control for controlling said switching circuit to output a channel of program information comprising combinations of the first and second programs information for output to a subscriber; means for selectively providing either the first or the second subscriber control information to the output channel from said switching circuit; and a scrambler coupled to said switching circuit for scrambling the subscriber control information and program information output from said switching circuit to the subscriber.

Claim 19

A headend apparatus comprising: program inputs for receiving first and second program information from a remote program source; inputs for receiving first and second subscriber control information from first and second control sources, said subscriber control information containing instruction that indicates to subscribers terminal to carry out a particular action; a switching circuit to which said first and second program information is applied; a switch control for controlling said switching circuit to one ore more output channels of program information comprising combinations of the first and second program information for output to a subscriber; means for selectively providing either the first or second subscriber control information to the channels output from said switching circuit; and a descrambler coupled to said program inputs for descrambling program information from said remote program source.

Claim 20

A headend apparatus comprising: program inputs for receiving first and second program information from a remote program source; inputs for receiving first and second subscriber control information from first and second control sources, said subscriber control information containing instruction that indicates to subscribers terminal to carry out a particular action; a switching circuit to which said first and second program information is applied; a switch control for controlling said switching circuit to one ore more output channels of program information comprising combinations of the first and second program information for output to a subscriber; means for selectively providing either the first or second subscriber control information to the channels output from said switching circuit; and a descrambler coupled to said program inputs for descrambling program information from said remote program source.

Claim 21

A headend apparatus comprising: a first input for receiving one or more first digital channels of program information from a first program source; a second input for receiving one or more second digital channels of program information from a second program source; a switching circuit to which the first and second digital channels of program information are applied; a switch control from controlling said switching circuit to output one or more third digital channels of program information comprising combinations of programs information of the first and second channels for distribution to a subscriber; wherein said first input receives first interleaved channels of time division multiplexed digital program information; and a 1:6 deinterleave circuit for deinterleaving the first interleaved channels of digital program information and outputting six channels of digital program information, each channel comprising a 5.6448 megabits per second data stream.

Claim 22

A headend apparatus comprising: a first input for receiving one or more first digital channels of program information from a first program source; a second input for receiving one or more second digital channels of program information from a second program source; a switching circuit to which the first and second digital channels of program information are applied; a switch control from controlling said switching circuit to output one or more third digital channels of program information comprising combinations of programs information of the first and second channels for distribution to a subscriber; wherein said first input receives first interleaved channels of time division multiplexed digital program information; and a 1:6 deinterleave circuit for deinterleaving the first interleaved channels of digital program information and outputting six channels of digital program information, each channel comprising a 5.6448 megabits per second data stream.

Claim 23

The headend apparatus according to claim 16 wherein each channel comprises five stations of interleaved digital program information.

Claim 24

A headend apparatus comprising: a first input for receiving one or more first digital channels of program information from a one or more program sources; a second input for receiving one or more second digital channels of program information from said one or more program sources; wherein said first input receives first interleaved channels of time division multiplexed digital program information and said second input receives second interleaved channels of time division multiplexed digital program information; a demultiplexing circuit receiving the interleaved digital program information of the first and second channels from the first and second input and outputting demultiplexed program information; a switching circuit to which the first and second demultiplexed digital channels of program information are applied; a switch control for controlling said switching circuit to output one or more third digital channels of program information comprising combinations of program information of the first and second channels for distribution to a subscriber; multiplexing circuit coupled to the output of said switching circuit for multiplexing the switched program information from said switching circuit to the third channels for distribution to the subscriber; and a scrambler coupled to the multiplexing circuit for scrambling the third channels.

Claim 25

A headend apparatus comprising: a first input for receiving one or more first digital channels of program information from a one or more program sources; a second input for receiving one or more second digital channels of program information from said one or more program sources; wherein said first input receives first interleaved channels of time division multiplexed digital program information and said second input receives second interleaved channels of time division multiplexed digital program information; a demultiplexing circuit receiving the interleaved digital program information of the first and second channels from the first and second input and outputting demultiplexed program information; a switching circuit to which the first and second demultiplexed digital channels of program information are applied; a switch control for controlling said switching circuit to output one or more third digital channels of program information comprising combinations of program information of the first and second channels for distribution to a subscriber; multiplexing circuit coupled to the output of said switching circuit for multiplexing the switched program information from said switching circuit to the third channels for distribution to the subscriber; and a scrambler coupled to the multiplexing circuit for scrambling the third channels.

Claim 26

A headend apparatus comprising: a first input for receiving one or more first digital channels of program information from a first program source; a second input for receiving one or more second digital channels of program information from a second program source; a switching circuit to which the first and second digital channels of program information are applied; a switch control for controlling said switching circuit to output one or more third digital channels of program information comprising combinations of programs information of the first and second channels for distribution to a subscriber; wherein said first input receives first interleaved channels of time division multiplexed digital program information and said second input receives second interleaved channels of time division multiplexed digital program information; demultiplexing circuits, comprising shift registers, receiving the interleaved digital program information of the first and second channels from the first and second input and outputting demultiplexed program information to said switching circuit; and multiplexing circuits coupled to the output of said switching circuit for multiplexing the program information from said switching circuit to the third channels for distribution to a subscriber.

Claim 27

A headend apparatus comprising: a first input for receiving one or more first digital channels of program information from a first program source; a second input for receiving one or more second digital channels of program information from a second program source; a switching circuit to which the first and second digital channels of program information are applied; a switch control for controlling said switching circuit to output one or more third digital channels of program information comprising combinations of programs information of the first and second channels for distribution to a subscriber; wherein said first input receives first interleaved channels of time division multiplexed digital program information and said second input receives second interleaved channels of time division multiplexed digital program information; demultiplexing circuits, comprising shift registers, receiving the interleaved digital program information of the first and second channels from the first and second input and outputting demultiplexed program information to said switching circuit; and multiplexing circuits coupled to the output of said switching circuit for multiplexing the program information from said switching circuit to the third channels for distribution to a subscriber.

Claim 28

A headend apparatus comprising: a first input for receiving one or more first digital channels of program information from a first program source; a second input for receiving one or more second digital channels of program information from a second program source; wherein said first input receives first interleaved channels of time division multiplexed digital program information and said second input receives second interleaved channels of time division multiplexed digital program information; demultiplexing circuits receiving the interleaved digital program information of the first and second channels received on the first and second input and outputting demultiplexed program information; a switching circuit to which the first and second digital channels of demultiplexed program information are applied; a switch control for controlling said switching circuit to output a plurality of digital channels of program information comprising combinations of programs information of the first and second channels; multiplexing circuits, comprising shift registers, coupled to the output of said switching circuit for multiplexing the plurality of digital channels of program information from said switching circuit to one or more third channels for distribution to a subscriber.

Claim 29

A headend apparatus comprising: a first input for receiving one or more first digital channels of program information from a first program source; a second input for receiving one or more second digital channels of program information from a second program source; wherein said first input receives first interleaved channels of time division multiplexed digital program information and said second input receives second interleaved channels of time division multiplexed digital program information; demultiplexing circuits receiving the interleaved digital program information of the first and second channels received on the first and second input and outputting demultiplexed program information; a switching circuit to which the first and second digital channels of demultiplexed program information are applied; a switch control for controlling said switching circuit to output a plurality of digital channels of program information comprising combinations of programs information of the first and second channels; multiplexing circuits, comprising shift registers, coupled to the output of said switching circuit for multiplexing the plurality of digital channels of program information from said switching circuit to one or more third channels for distribution to a subscriber.

Claim 32

A headend apparatus comprising: a first input for receiving one or more first digital channel of time division multiplexed program information and control information from a first source; a second input for receiving a second digital channel of control information from a second source; a switching circuit to which information within the first digital channels and second digital channel are applied; a switch control for controlling said switching circuit to output one or more third digital channels of information, each of said third channels comprising combinations program information of the first channels and control information from the second channels for distribution to a subscriber; said switching circuit including means for replacing the control information in the first digital channels with the control information in the second digital channel when outputting the one or more third channels; and a scrambler coupled to an output of the switching circuit for scrambling the third channel.

Claim 33

A headend apparatus comprising: a first input for receiving one or more first digital channel of time division multiplexed program information and control information from a first source; a second input for receiving a second digital channel of control information from a second source; a switching circuit to which information within the first digital channels and second digital channel are applied; a switch control for controlling said switching circuit to output one or more third digital channels of information, each of said third channels comprising combinations program information of the first channels and control information from the second channels for distribution to a subscriber; said switching circuit including means for replacing the control information in the first digital channels with the control information in the second digital channel when outputting the one or more third channels; and a scrambler coupled to an output of the switching circuit for scrambling the third channel.

Claim 34

The headend apparatus as recited in claim 22 wherein said first input receives first interleaved channels of time division multiplexed digital information comprising a 33.8688 megabits per second data stream.