US5550823A
Expired / Lapsed
US
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Method and apparatus for performing priority control for cells in output buffer type ATM switch
Assignee: NEC Corp
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Filing: 1995-04-28
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Granted: 1996-08-27
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Expires: 2015-04-28
Abstract
Abstract There is provided a method of performing priority control for cells in an output buffer type ATM switch including a switching unit, having a plurality of input ports and a plurality of output ports, for switching/outputting the cells input from the input ports to the output ports in accordance with routing information, and a plurality of output buffer units having output buffer memories, connected to the output ports of the switching unit, for temporarily storing the cells output from the output ports to perform output control of the cells. A loss quality class, a delay quality class and the routing information are added to each of the cells. A plurality of logical queues for temporarily storing the cells are virtually set in an input buffer memory in accordance with the delay quality classes and the routing information. The input cells are selectively written in the logical queues on the basis of the loss quality classes and the routing information added to the cells. A transition process is performed for all the logical queues to change the delay quality class of each of the logical queues into one of upper and lower classes depending on a cell storage amount in the logical queue. Upon completion of the transition process, the cells are read from the logical queue having the delay quality class which is an uppermost class.
Inventors
- 👤 Yasuhito Irie
- 👤 Kenji Yamada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 11:40
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/54; H04L12/56; H04L12/5601; H04L49/00; H04L49/30; H04L49/3081; H04L49/10; H04L49/104; H04L49/105; H04L49/3027; H04L2012/5638; H04L2012/5646; H04L2012/5651; H04L2012/5678; H04L2012/5681; H04L49/55
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
222 words
A method of performing priority control for cells in an output buffer type ATM switch including a switching unit, having a plurality of input ports and a plurality of output ports, for switching/outputting the cells input from said input ports to said output ports in accordance with routing information, and a plurality of output buffer units having output buffer memories, connected to said output ports of said switching unit, for temporarily storing the cells output from said output ports to perform output control of the cells, comprising the steps of: adding a loss quality class, a delay quality class and the routing information to each of the cells; virtually setting a plurality of logical queues, for temporarily storing the cells, in input buffer memories in accordance with the delay quality classes and the routing information; selectively writing the input cells in said logical queues on the basis of the loss quality classes and the routing information added to the cells; performing a transition process for all said logical queues to change the delay quality class of each of said logical queues into one of upper and lower classes depending on a cell storage amount in said logical queue; and upon completion of the transition process, reading the cells from said logical queue having the delay quality class which is an uppermost class.
Claim 2
Independent Claim
222 words
A method of performing priority control for cells in an output buffer type ATM switch including a switching unit, having a plurality of input ports and a plurality of output ports, for switching/outputting the cells input from said input ports to said output ports in accordance with routing information, and a plurality of output buffer units having output buffer memories, connected to said output ports of said switching unit, for temporarily storing the cells output from said output ports to perform output control of the cells, comprising the steps of: adding a loss quality class, a delay quality class and the routing information to each of the cells; virtually setting a plurality of logical queues, for temporarily storing the cells, in input buffer memories in accordance with the delay quality classes and the routing information; selectively writing the input cells in said logical queues on the basis of the loss quality classes and the routing information added to the cells; performing a transition process for all said logical queues to change the delay quality class of each of said logical queues into one of upper and lower classes depending on a cell storage amount in said logical queue; and upon completion of the transition process, reading the cells from said logical queue having the delay quality class which is an uppermost class.
Claim 3
Dependent Claim
102 words
A method according to claim 1, wherein the step of performing the transition process comprises the steps of: checking whether a current cell storage amount in each of said logical queues exceeds a predetermined cell storage threshold corresponding to an initial delay quality class preset in said logical queues; changing a delay quality cell of said selected logical queue into an upper class when the cell storage amount exceeds the cell storage threshold; and changing the delay quality class of the logical queue into the initial delay quality class when the cell storage amount is not larger than the cell storage threshold.
Claim 4
Dependent Claim
80 words
A method according to claim 1, further comprising the steps of: checking whether a cell storage amount in said output buffer units exceeds a predetermined cell storage threshold; and when the cell storage amount exceeds the cell storage threshold, changing a delay quality class of said logical queue, corresponding to an output port of said switching unit connected to said output buffer unit representing that the cell storage amount exceeds the cell storage threshold, into a lowest delay quality class.
Claim 5
Dependent Claim
39 words
A method according to claim 3, wherein the lowest delay quality class is a read inhibition class, and read access of cells from said logical queue having a delay quality class changed into the read inhibition class is inhibited.
Claim 6
Dependent Claim
94 words
A method according to claim 1, wherein the step of selectively writing the input cells in said logical queues, comprises the steps of: checking whether the cell storage amount in said logical queue selected on the basis of the delay quality classes and the routing information exceeds a loss threshold corresponding to the loss quality class added to the cell; causing a cell loss when the cell storage amount exceeds the loss threshold; and writing the cell in said selected logical queue when the cell storage amount is not larger than the loss threshold.
Claim 7
Dependent Claim
59 words
A method according to claim 1, wherein the step of reading the cells from said logical queue comprises the step of, when a plurality of logical queues each having an uppermost delay quality class are present, selecting said logical queues each having the uppermost delay quality class in a predetermined order to sequentially read cells from said logical queues.
Claim 8
Dependent Claim
221 words
A priority control apparatus for cells in an output buffer type ATM switch, comprising: switching means, including a plurality of input ports and a plurality of output ports, for selecting/outputting the cells input from said input ports to said output ports in accordance with routing information of the cells to which loss quality classes and delay quality classes are added; a plurality of buffer means having output buffer memories, connected to said output ports of said switching means, for temporarily storing the cells output from said output ports to perform output control for the cells; a plurality of logical queues, virtually set in input buffer memories in accordance with the delay quality classes and the routing information, for temporarily storing the cells; write control means for performing write control for writing the input cells in said logical queues on the basis of the loss quality classes and the routing information added to the cells; and read control means, respectively, arranged for said input ports of said switching means, for performing read control for reading the cells from said logical queue having the delay quality class changed into an uppermost class after a delay quality class of each of all said logical queues is changed into one of upper and lower classes depending on a cell storage amount in said logical queue.
Claim 9
Dependent Claim
221 words
A priority control apparatus for cells in an output buffer type ATM switch, comprising: switching means, including a plurality of input ports and a plurality of output ports, for selecting/outputting the cells input from said input ports to said output ports in accordance with routing information of the cells to which loss quality classes and delay quality classes are added; a plurality of buffer means having output buffer memories, connected to said output ports of said switching means, for temporarily storing the cells output from said output ports to perform output control for the cells; a plurality of logical queues, virtually set in input buffer memories in accordance with the delay quality classes and the routing information, for temporarily storing the cells; write control means for performing write control for writing the input cells in said logical queues on the basis of the loss quality classes and the routing information added to the cells; and read control means, respectively, arranged for said input ports of said switching means, for performing read control for reading the cells from said logical queue having the delay quality class changed into an uppermost class after a delay quality class of each of all said logical queues is changed into one of upper and lower classes depending on a cell storage amount in said logical queue.
Claim 10
Dependent Claim
106 words
An apparatus according to claim 7, wherein said read control means comprises: determining means for checking whether a current cell storage amount in each of said logical queues exceeds a predetermined cell storage threshold corresponding to an initial delay quality class preset in said logical queues; and delay quality class transition means for changing a delay quality class of said selected logical queue into an upper class when the cell storage amount exceeds the cell storage threshold, and changing the delay quality class of said logical queue into the initial delay quality class when the cell storage amount is not larger than the cell storage threshold.
Claim 11
Dependent Claim
77 words
An apparatus according to claim 7, further comprising: determining means for checking whether the cell storage amount in each of said output buffer means exceeds a predetermined storage threshold; and delay quality class transition means for changing a delay quality class of said logical queue, corresponding to an output port of said switching means connected to said output buffer means representing that the cell storage amount exceeds the cell storage threshold, into a lowest delay quality class.
Claim 12
Dependent Claim
42 words
An apparatus according to claim 9, wherein the lowest delay quality class is a read inhibition class, and said read control means inhibits cells from being read from said logical queue having a delay quality class changed into the read inhibition class.
Claim 13
Dependent Claim
96 words
An apparatus according to claim 7, wherein said write control means comprises the steps of: determining means for checking whether the cell storage amount in said logical queue selected on the basis of the delay quality classes and the routing information exceeds a loss threshold corresponding to the loss quality class added to the cell; cell loss means for causing a cell loss when the cell storage amount exceeds the loss threshold; and writing means for writing the cell in said selected logical queue when the cell storage amount is not larger than the loss threshold.
Claim 14
Dependent Claim
52 words
An apparatus according to claim 7, wherein read control means comprises selecting means for selecting said logical queues each having the uppermost delay quality class in a predetermined order to sequentially reading cells from said logical queues when a plurality of logical queues each having an uppermost delay quality class are present.
Claim 15
Dependent Claim
39 words
An apparatus according to claim 7, wherein said switching means and said output buffer means constitute an output buffer type ATM switch, and said logical queues, said write control means, and read control means constitute an input buffer unit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-27 | 2000-02-26 | 2000-08-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-27 | 2004-02-26 | 2004-08-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-27 | 2008-02-26 | 2008-08-27 | $7700.00 | Window Closed / Lapsed |