MOS gate driver integrated circuit for ballast circuits

Claim 2

A monolithic integrated circuit formed in a silicon substrate for driving first and second MOS gated power devices which are connected in a half bridge circuit which has first and second d-c terminals and a common terminal at the node between said first and second MOS gated power devices; said monolithic integrated circuit including timer circuit means having an input control terminal C T which is connectable to a low logic level signal referenced to the potential of said substrate; latch circuit means coupled to said timer circuit means for controlling the frequency at which said first and second MOS gated power devices are switched on and off and having an output which is switched in response to a predetermined signal applied to said input control terminal; a high side dead time delay circuit and a low side dead time delay circuit each coupled to said latch circuit means for delaying the transmission of a latch output signal for a predetermined time delay following the switching of the output of said latch circuit means; a high side level shifting means and a high side driver circuit means and a low side driver circuit means; said high side driver circuit means and said low side driver circuit means coupled to said high side dead time circuit and said low side dead time circuit, respectively, and having high side and low side output pins, respectively, which produce outputs for turning on and off said first and second MOS gated power devices in response to control signals at said input control terminal C T ; said high side and low side dead time delay circuits preventing the simultaneous conduction of said first and second MOS gated power devices; and an undervoltage circuit monitor means coupled to said high side driver circuit means and low side driver circuit means to disable said high side and low side driver circuit means as a function of an operating voltage V cc and a control voltage, said undervoltage circuit monitor means disabling said high side and said low side driver circuit means when said operating voltage is less than a first predetermined value during an initial startup of said half bridge circuit, said undervoltage circuit monitor means enabling said low side driver circuit means and supplying said control voltage to said input control terminal C T when said operating voltage is greater than said first predetermined value and less than a second predetermined value, and said undervoltage circuit monitor means disabling said low side driver circuit means and enabling said high side driver circuit means when said control voltage is greater than a third predetermined value, thereby protecting said first and second MOS gated power devices.

Claim 3

The integrated circuit of claim 1 wherein said MOS gated power devices are MOS devices which are selected from the group consisting of power MOSFETs, IGBTs and MOS gated thyristors.

Claim 4

The integrated circuit of claim 1 wherein said predetermined time delay varies from about 100 nanoseconds to 10 microseconds.

Claim 5

The integrated circuit of claim 1 which further includes a source of said operating voltage V cc coupled to said first and second d-c terminals for providing operating power for each of said low side and high side driver circuit means in said integrated circuit; said integrated circuit having a V cc pin extending therefrom for connection to at least one of said first or second d-c terminals.

Claim 6

The circuit of claim 4 which further includes resistor means for coupling said V cc pin to said first d-c terminal.

Claim 7

The integrated circuit of claim 4 wherein said low side under-voltage circuit monitor means is coupled to and monitors the voltage at said V cc pin and has an output coupled to said latch circuit means and to said high side and low side dead time circuits for disabling said latch circuit means and delay circuits when the voltage at said V cc pin falls below a given value.

Claim 8

The integrated circuit of claim 6 wherein said predetermined time delay is from 100 nanoseconds to 10 microseconds.

Claim 9

The integrated circuit of claim 2 which further includes a source of said operating voltage Vcc coupled to said first and second d-c terminals for providing operating power for each of said low side and high side driver circuit means in said integrated circuit, said integrated circuit having a V cc pin extending therefrom for connection to at least one of said first or second d-c terminals.

Claim 10

The circuit of claim 8 which further includes resistor means for coupling said V cc pin to said first d-c terminal.

Claim 11

An electronic ballast circuit including, in combination, at least one gas discharge lamp, at least one L-C circuit in series with said gas discharge lamp, first and second series connected MOS gate controlled power switching devices having respective gate terminals and connected in a half bridge circuit arrangement and formed in a substrate, a pair of d-c power terminals connected in series with said first and second series connected switching devices; said lamp and L-C series circuit connected across said second MOS gate controlled power switching device; and a monolithic gate drive circuit having an input terminal for receiving input logic level signals for alternately switching on and off both of said first and second MOS gated controlled power switching devices at a given frequency of oscillation; said monolithic gate drive circuit having output terminals H 0 and L 0 coupled to the respective gates of said MOS gate power switching devices; said gate drive circuit having a terminal V cc which provides the operating power for its internal circuitry; and an external resistor for connecting said terminal V cc to one of said pair of terminals; said monolithic integrated circuit including timer circuit means having an input control terminal C T which is connectable to a low logic level signal referenced to the potential of said substrate; latch circuit means coupled to said timer circuit means for controlling the frequency at which said first and second MOS gated power switching devices are switched on and off and having an output which is switched in response to a predetermined signal affixed to said input control terminal; a high side dead time delay circuit and a low side dead time circuit each coupled to said latch circuit means for delaying the transmission of a latch output signal for a predetermined time delay following the switching of the output of said latch circuit means; a high side level shifting means and a high side driver circuit means and a low side driver circuit means; said high side driver circuit means and said low side driver circuit means coupled to said high side dead time circuit and said low side dead time circuit, respectively, and having high side and low side output pins, respectively, which produce outputs for turning on and off said first and second MOS gated power devices in response to control signals at said input control terminal C T ; said dead time delay circuits preventing the simultaneous conduction of said first and second MOS gated power switching devices; and an undervoltage circuit monitor means coupled to said high side driver circuit means and low side driver circuit means, respectively, to disable said high side and low side driver circuits as a function of an operating voltage supplied to said terminal V cc and a control voltage; said undervoltage circuit monitor means disabling said high side and said low side driver circuits when said operating voltage is less than a first predetermined value during an initial startup of said half bridge circuit, said undervoltage circuit monitor means enabling said low side driver circuit and supplying said control voltage to said input control terminal C T when said operating voltage is greater than said first predetermined value and less than a second predetermined value, and said undervoltage circuit monitor means disabling said low side driver circuit and enabling said high side driver circuit when said control voltage is greater than a third predetermined value, thereby preventing damage to said electronic ballast circuit by protecting said first and second MOS gated power switching devices.

Claim 12

An electronic ballast circuit including, in combination, at least one gas discharge lamp, at least one L-C circuit in series with said gas discharge lamp, first and second series connected MOS gate controlled power switching devices having respective gate terminals and connected in a half bridge circuit arrangement and formed in a substrate, a pair of d-c power terminals connected in series with said first and second series connected switching devices; said lamp and L-C series circuit connected across said second MOS gate controlled power switching device; and a monolithic gate drive circuit having an input terminal for receiving input logic level signals for alternately switching on and off both of said first and second MOS gated controlled power switching devices at a given frequency of oscillation; said monolithic gate drive circuit having output terminals H 0 and L 0 coupled to the respective gates of said MOS gate power switching devices; said gate drive circuit having a terminal V cc which provides the operating power for its internal circuitry; and an external resistor for connecting said terminal V cc to one of said pair of terminals; said monolithic integrated circuit including timer circuit means having an input control terminal C T which is connectable to a low logic level signal referenced to the potential of said substrate; latch circuit means coupled to said timer circuit means for controlling the frequency at which said first and second MOS gated power switching devices are switched on and off and having an output which is switched in response to a predetermined signal affixed to said input control terminal; a high side dead time delay circuit and a low side dead time circuit each coupled to said latch circuit means for delaying the transmission of a latch output signal for a predetermined time delay following the switching of the output of said latch circuit means; a high side level shifting means and a high side driver circuit means and a low side driver circuit means; said high side driver circuit means and said low side driver circuit means coupled to said high side dead time circuit and said low side dead time circuit, respectively, and having high side and low side output pins, respectively, which produce outputs for turning on and off said first and second MOS gated power devices in response to control signals at said input control terminal C T ; said dead time delay circuits preventing the simultaneous conduction of said first and second MOS gated power switching devices; and an undervoltage circuit monitor means coupled to said high side driver circuit means and low side driver circuit means, respectively, to disable said high side and low side driver circuits as a function of an operating voltage supplied to said terminal V cc and a control voltage; said undervoltage circuit monitor means disabling said high side and said low side driver circuits when said operating voltage is less than a first predetermined value during an initial startup of said half bridge circuit, said undervoltage circuit monitor means enabling said low side driver circuit and supplying said control voltage to said input control terminal C T when said operating voltage is greater than said first predetermined value and less than a second predetermined value, and said undervoltage circuit monitor means disabling said low side driver circuit and enabling said high side driver circuit when said control voltage is greater than a third predetermined value, thereby preventing damage to said electronic ballast circuit by protecting said first and second MOS gated power switching devices.

Claim 13

The integrated circuit of claim 1 wherein said undervoltage circuit monitor means comprises first undervoltage circuit monitor means coupled to said high side driver circuit means and second undervoltage circuit monitor means coupled to said low side driver circuit means.

Claim 14

The integrated circuit of claim 1 wherein said undervoltage circuit monitor means disables said high side and said low side driver circuits when said operating voltage falls below a fourth predetermined value during a powerdown of said half bridge circuit.

Claim 15

The electronic ballast circuit of claim 10 wherein said undervoltage circuit monitor means comprises first undervoltage circuit monitor means coupled to said high side driver circuit means and second undervoltage circuit monitor means coupled to said low side driver circuit means.

Claim 16

The electronic ballast circuit of claim 10 wherein said undervoltage circuit monitor means disables said high side and said low side driver circuits when said operating voltage falls below a fourth predetermined value during a powerdown of said half bridge circuit.

Claim 17

The electronic ballast circuit of claim 10 further comprising charge pumping means for controlling said operating voltage as a function of an output voltage supplied to said lamp and said L-C series circuit.

Claim 18

The electronic ballast circuit of claim 15 wherein said L-C series circuit includes an inductor that forms a primary winding of a transformer, and said charge pumping means includes a secondary winding of said transformer.

Claim 19

A monolithic integrated circuit formed in a silicon substrate for driving first and second MOS gated power devices which are connected in a half bridge circuit which has first and second d-c terminals and a common terminal at the node between said first and second MOS gated power devices; said monolithic integrated circuit including timer circuit means having an input control terminal C T which is connectable to a low logic level signal referenced to the potential of said substrate; latch circuit means coupled to said timer circuit means for controlling the frequency at which said first and second MOS devices are switched on and off and having an output which is switched in response to a predetermined signal applied to said input control terminal; a high side dead time delay circuit and a low side dead time delay circuit each coupled to said latch circuit means for delaying the transmission of a latch output signal for a predetermined time delay following the switching of the output of said latch circuit means; a high side level shifting means and a high side driver circuit means and a low side driver circuit means; said high side driver circuit means and said low side driver means coupled to said high side dead time circuit and said low side dead time circuit, respectively, and having high side and low side output pins, respectively, which produce outputs for turning on and off said first and second MOS gated power devices in response to control signals at said input control terminal C T ; said dead time delay circuits preventing the simultaneous conduction of said first and second MOS gated power devices; and an undervoltage circuit monitor means coupled to said high side driver circuit means and low side driver circuit means, respectively, to disable said high side and low side driver circuits as a function of an operating voltage V cc and a control voltage to protect said first and second MOS gated power devices; said undervoltage circuit monitor means comprising means for disabling said high side and said low side driver circuits when said operating voltage is less than a first predetermined value during an initial startup of said half bridge circuit, means for enabling said low side driver circuit and for supplying said control voltage to said input control terminal C T when said operating voltage is greater than said first predetermined value and less than a second predetermined value, and means for disabling said low side driver circuit and for enabling said high side driver circuit when said control voltage is greater than a third predetermined value.

Claim 20

A monolithic integrated circuit formed in a silicon substrate for driving first and second MOS gated power devices which are connected in a half bridge circuit which has first and second d-c terminals and a common terminal at the node between said first and second MOS gated power devices; said monolithic integrated circuit including timer circuit means having an input control terminal C T which is connectable to a low logic level signal referenced to the potential of said substrate; latch circuit means coupled to said timer circuit means for controlling the frequency at which said first and second MOS devices are switched on and off and having an output which is switched in response to a predetermined signal applied to said input control terminal; a high side dead time delay circuit and a low side dead time delay circuit each coupled to said latch circuit means for delaying the transmission of a latch output signal for a predetermined time delay following the switching of the output of said latch circuit means; a high side level shifting means and a high side driver circuit means and a low side driver circuit means; said high side driver circuit means and said low side driver means coupled to said high side dead time circuit and said low side dead time circuit, respectively, and having high side and low side output pins, respectively, which produce outputs for turning on and off said first and second MOS gated power devices in response to control signals at said input control terminal C T ; said dead time delay circuits preventing the simultaneous conduction of said first and second MOS gated power devices; and an undervoltage circuit monitor means coupled to said high side driver circuit means and low side driver circuit means, respectively, to disable said high side and low side driver circuits as a function of an operating voltage V cc and a control voltage to protect said first and second MOS gated power devices; said undervoltage circuit monitor means comprising means for disabling said high side and said low side driver circuits when said operating voltage is less than a first predetermined value during an initial startup of said half bridge circuit, means for enabling said low side driver circuit and for supplying said control voltage to said input control terminal C T when said operating voltage is greater than said first predetermined value and less than a second predetermined value, and means for disabling said low side driver circuit and for enabling said high side driver circuit when said control voltage is greater than a third predetermined value.

Claim 21

The integrated circuit of claim 17 wherein said undervoltage circuit monitor means further comprises means for disabling said high side and said low side driver circuits when said operating voltage falls below a fourth predetermined value during a powerdown of said half bridge circuit.

Claim 22

The integrated circuit of claim 17 wherein said MOS gated power devices are MOS devices which are selected from the group consisting of power MOSFETs, IGBTs and MOS gated thyristors.

Claim 23

The integrated circuit of claim 17 wherein said predetermined time delay varies from about 100 nanoseconds to 10 microseconds.