Equal length symmetric computer bus topology

Claim 2

In a computer system, a computer bus system for transmitting a plurality of bus signals, said computer bus system comprising: a single multi-layered printed circuit board; a plurality of physically parallel bus connectors on said single multi-layered printed circuit board, each of said physically parallel bus connectors for transmitting and receiving said plurality of bus signals; a plurality of bus signal paths on said single multi-layered printed circuit board, each bus signal path carrying one of said bus signals, each of said bus signal paths comprising, a passive central junction point; and a plurality of transmission paths, said plurality of transmission paths extending from said passive central junction point to each of said physically parallel bus connectors such that every bus connector is coupled to said passive central junction point, each of said transmission paths having an equal length.

Claim 3

The computer bus system as claimed in claim 1 wherein each of said transmission paths have identical electrical properties.

Claim 4

The computer bus system as claimed in claim 1 wherein each of said physically parallel bus connectors have identical electrical properties.

Claim 5

The computer bus system as claimed in claim 1 wherein said plurality of physically parallel bus connectors are also electrically parallel to one another.

Claim 6

The computer bus system as claimed in claim 4 wherein said passive central junction point for each of said bus signal paths is centered between said plurality of physically parallel bus connectors.

Claim 7

The computer bus system claimed in claim 5 wherein said bus signal paths comprise printed circuit board traces on said multi-layered single printed circuit board.

Claim 8

The computer bus system as claimed in claim 6 wherein said printed circuit board traces are routed in a serpentine pattern.

Claim 9

The computer bus system as claimed in claim 7 wherein said bus comprises a Micro Channel Bus.

Claim 10

The computer bus system as claimed in claim 7 wherein said multi-layered printed circuit board traces are of a thickness D and said printed circuit board traces are at least a distance 3D apart from each other.

Claim 13

The method of constructing a computer bus system as claimed in claim 10 wherein each of said plurality of electrical lines have identical electrical properties.

Claim 14

The method of constructing a computer bus system as claimed in claim 10 wherein each of said physically parallel bus nodes have identical electrical properties.

Claim 15

The method of constructing a computer bus system as claimed in claim 10 wherein the step of placing a passive central junction point for each bus signal further comprises centering said passive central junction point between said plurality of physically parallel bus connectors.

Claim 16

The method of constructing a computer bus system as claimed in claim 13 wherein the step of electrically connecting each of said passive central junction points to each of said physically parallel bus connectors comprises etching traces on said single multi-layered printed circuit board.

Claim 17

The method of constructing a computer bus system as claimed in claim 14 wherein the step of electrically connecting each of said passive central junction points to each of said physically parallel bus connectors comprises routing said multi-layered printed circuit board traces in a serpentine pattern.

Claim 18

The method of constructing a computer bus system as claimed in claim 15 wherein each of said physically parallel bus connectors comprise a Micro-channel bus connector.

Claim 19

The method of constructing a computer bus system as claimed in claim 14 wherein said printed circuit board traces are of a thickness D and said multi-layered printed circuit board traces are at least a distance 3D apart from each other.

Claim 20

A computer system with a computer bus system that minimizes the effect of transmission line reflections, said computer system comprising: a single multi-layered printed circuit motherboard; a computer bus on said multi-layered single printed circuit motherboard, said computer bus transmitting a plurality of bus signals to a plurality of physically parallel bus connectors on said single multi-layered printed circuit motherboard, each of said physically parallel bus connectors for transmitting and receiving said bus signals, each of said bus signals carried on a bus signal path, each of said bus signal paths bus comprising: a passive central junction point, said passive central junction point centered between said plurality of physically parallel bus connectors; a plurality of transmission paths, said plurality of transmission paths extending from said passive central junction point to each of said plurality of physically parallel bus connectors such that every physically parallel bus connector is coupled to said passive central junction point, each of said transmission paths having an equal length; a processor coupled to said computer bus system, said processor being one of said physically parallel bus connectors; and a memory unit coupled to said computer bus system, said memory unit being one of said physically parallel bus connectors.

Claim 21

A computer system with a computer bus system that minimizes the effect of transmission line reflections, said computer system comprising: a single multi-layered printed circuit motherboard; a computer bus on said multi-layered single printed circuit motherboard, said computer bus transmitting a plurality of bus signals to a plurality of physically parallel bus connectors on said single multi-layered printed circuit motherboard, each of said physically parallel bus connectors for transmitting and receiving said bus signals, each of said bus signals carried on a bus signal path, each of said bus signal paths bus comprising: a passive central junction point, said passive central junction point centered between said plurality of physically parallel bus connectors; a plurality of transmission paths, said plurality of transmission paths extending from said passive central junction point to each of said plurality of physically parallel bus connectors such that every physically parallel bus connector is coupled to said passive central junction point, each of said transmission paths having an equal length; a processor coupled to said computer bus system, said processor being one of said physically parallel bus connectors; and a memory unit coupled to said computer bus system, said memory unit being one of said physically parallel bus connectors.

Claim 22

The computer system as claimed in claim 18 wherein each of said transmission paths have substantially identical electrical characteristics.

Claim 23

The computer system as claimed in claim 19 wherein said transmission paths comprise printed circuit board traces on said multi-layered printed circuit motherboard.