Destuff circuit for asynchronous digital signals

Claim 2

A destuff circuit comprising: a buffer memory for temporarily storing received data of a channel after stuffed dummy data are eliminated from received data; a read address counter for generating read address signals for reading data stored in said buffer memory; and a virtual write address generator for generating a virtual write address signal based on an average value Yn wherein total number of destuff control pulses in a period T is assumed to be said average value Yn of actually occurred destuff control pulses over the latest n periods (that is in a duration nT), and change of output of said read address is phase-locked with change of output of said virtual write address generator.

Claim 3

A destuff circuit of claim 1, wherein said virtual write address generator comprises: a gate pulse generator for generating a train of pulses with a pulse repetition period T; means for producing an averaged number Yn of destuff control pulses included in said received data for each period of T, averaged over latest nT duration; gate means for deleting Yn clock pulses in each cycle of T, from address clock pulses generated by bit clocks extracted from received digital signals of said channel, and a virtual write address counter for counting output pulses from said gate means.

Claim 4

A destuff circuit of claim 2, wherein said period T generated by said gate pulse generator is controlled by said averaged number Yn, and by output of a phase detector for detecting time lag from a time of generation of a write address at said write address counter to a time of generation of a corresponding read address at said read address counter.

Claim 5

A destuff circuit of claim 3, wherein said cycle T produced by said gate pulse generator is controlled in a range from several milliseconds to several seconds.

Claim 6

A destuff circuit comprising: a buffer memory for temporarily storing received data of a channel after stuffed dummy data are eliminated from received data; a read address counter for generating read address signals for reading data stored in said buffer memory; a gate pulse generator for generating a train of pulses with a pulse repetition period T; means for producing an averaged number Yn of destuff control pulses included in said received data for each cycle of T, averaged over latest nT duration; gate means for deleting Yn clock pulses in each period of T, from address clock pulses generated by bit clocks extracted from received digital signals of said channel; a virtual write address counter for counting output pulses from said gate means; and means for controlling said period T by said averaged number Yn, and by output of a phase detector for detecting time lag from a time of generation of a write address at said write address counter to a time of generation of a corresponding read address at said read address counter, T being increased when Yn is small and T being decreased when said time lag is small.

Claim 7

A destuff circuit comprising: a buffer memory for temporarily storing received data of a channel after stuffed dummy data are eliminated from received data; a read address counter for generating read address signals for reading data stored in said buffer memory; a gate pulse generator for generating a train of pulses with a pulse repetition period T; means for producing an averaged number Yn of destuff control pulses included in said received data for each cycle of T, averaged over latest nT duration; gate means for deleting Yn clock pulses in each period of T, from address clock pulses generated by bit clocks extracted from received digital signals of said channel; a virtual write address counter for counting output pulses from said gate means; and means for controlling said period T by said averaged number Yn, and by output of a phase detector for detecting time lag from a time of generation of a write address at said write address counter to a time of generation of a corresponding read address at said read address counter, T being increased when Yn is small and T being decreased when said time lag is small.