US5548285A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit and method of indicating data hold-time
Assignee: ADZUKI FOUNDATION Pte LLC
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Filing: 1994-07-18
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Granted: 1996-08-20
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Expires: 2014-07-18
Abstract
Abstract A parallel to serial converter (10) uses a data hold-time indicator (22) to indirectly observe the timing relationship of the data and clock applied to a data register (14) embedded within an integrated circuit. The incoming data word is converted from CMOS to ECL logic levels (12) and applied to the data register. The register holds data for a multiplexer (16) that rotates through the output data from the register for providing a serial data output signal. A flipflop circuit (18) clocks the serial data output signal. The data hold-time indicator circuit monitors one register input and generates a recurring pulse having a width that reflects the data hold-time at the embedded register. By indirectly observing the timing relationship, the externally sourced data timing can be calibrated to meet the setup and hold-time requirements of the data register.
Inventors
- 👤 David K. Ford
- 👤 Bernard E. Weir, III
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 18:09
CPC Classifications
H; H03; H03M; H03M9/00; H03K; H03K5/00; H03K5/153; H03K5/1534
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
147 words
A data hold-time indicator circuit, comprising: a first flipflop having a data input, a clock input, a reset input and an output, said data input being coupled for receiving a data input signal, said clock input being coupled for receiving a clock signal, said reset input being coupled for receiving an inverted data input signal; a second flipflop having a data input, a clock input, a reset input and an output, said data input being coupled for receiving said inverted data input signal, said clock input being coupled for receiving said clock signal, said reset input being coupled for receiving said data input signal; and a logic gate having first and second inputs and an output, said first input being coupled to said output of said first flipflop, said second input being coupled to said output of said second flipflop, said output providing a data hold-time signal.
Claim 2
Dependent Claim
147 words
A data hold-time indicator circuit, comprising: a first flipflop having a data input, a clock input, a reset input and an output, said data input being coupled for receiving a data input signal, said clock input being coupled for receiving a clock signal, said reset input being coupled for receiving an inverted data input signal; a second flipflop having a data input, a clock input, a reset input and an output, said data input being coupled for receiving said inverted data input signal, said clock input being coupled for receiving said clock signal, said reset input being coupled for receiving said data input signal; and a logic gate having first and second inputs and an output, said first input being coupled to said output of said first flipflop, said second input being coupled to said output of said second flipflop, said output providing a data hold-time signal.
Claim 3
Dependent Claim
33 words
The data hold-time indicator circuit of claim 1 further including an inverter having an input coupled for receiving said data input signal and having an output for providing said inverted data input signal.
Claim 4
Independent Claim
61 words
A method of observing timing relationship between a clock signal and a data signal, comprising the steps of: detecting a clocking edge of the clock signal; detecting a transition of the data signal; and generating a hold-time indicator pulse having a duration determined by a difference between said clocking edge of the clock signal and said transition of the data signal.
Claim 5
Independent Claim
61 words
A method of observing timing relationship between a clock signal and a data signal, comprising the steps of: detecting a clocking edge of the clock signal; detecting a transition of the data signal; and generating a hold-time indicator pulse having a duration determined by a difference between said clocking edge of the clock signal and said transition of the data signal.
Claim 6
Dependent Claim
26 words
The method of claim 3 wherein said step of generating a hold-time indicator pulse includes the step of setting the data signal to a first state.
Claim 7
Dependent Claim
39 words
The method of claim 4 wherein said step of generating a hold-time indicator pulse includes the step of storing said first state of the data signal in a first flipflop upon receiving said clocking edge of said clock signal.
Claim 8
Dependent Claim
33 words
The method of claim 5 wherein said step of generating a hold-time indicator pulse further includes the step of resetting a second flipflop in response to said first state of the data signal.
Claim 9
Dependent Claim
43 words
The method of claim 6 wherein said step of generating a hold-time indicator pulse further includes the step of combining output signals of said first and second flipflops with a logical OR operation to generate a first edge of said hold-time indicator pulse.
Claim 10
Dependent Claim
27 words
The method of claim 7 wherein said step of generating a hold-time indicator pulse further includes the step of changing the data signal to a second state.
Claim 11
Dependent Claim
33 words
The method of claim 8 wherein said step of generating a hold-time indicator pulse further includes the step of resetting said first flipflop in response to said second state of the data signal.
Claim 12
Dependent Claim
44 words
The method of claim 9 wherein said step of generating a hold-time indicator pulse further includes the step of combining said output signals of said first and second flipflops with a logical OR operation to generate a second edge of said hold-time indicator pulse.
Claim 13
Dependent Claim
109 words
A parallel to serial converter circuit, comprising: a register having inputs receiving a data word, said register loading said data word in response to a register clock signal; a multiplexer having inputs coupled to outputs of said register, said multiplexer rotating through said inputs in response to a multiplexer control signal for providing serial data signals at an output; and circuit means having an input receiving one bit of said data word and said clock signal for generating a hold-time pulse having a duration determined by a difference between a clocking edge of said register clock signal and a trailing edge of said one bit of said data word.
Claim 14
Dependent Claim
109 words
A parallel to serial converter circuit, comprising: a register having inputs receiving a data word, said register loading said data word in response to a register clock signal; a multiplexer having inputs coupled to outputs of said register, said multiplexer rotating through said inputs in response to a multiplexer control signal for providing serial data signals at an output; and circuit means having an input receiving one bit of said data word and said clock signal for generating a hold-time pulse having a duration determined by a difference between a clocking edge of said register clock signal and a trailing edge of said one bit of said data word.
Claim 15
Dependent Claim
150 words
The parallel to serial converter circuit of claim 11 wherein said circuit means includes: a first flipflop having a data input, a clock input, a reset input and an output, said data input receiving said one bit of said data word, said clock input receiving said register clock signal, said reset input receiving an inverted one bit of said data word; a second flipflop having data input, a clock input, a reset input and an output, said data input receiving said inverted one bit of said data word, said clock input receiving said register clock signal, said reset input receiving said one bit of said data word; and a logic gate having first and second inputs and an output, said first input being coupled to said output of said first flipflop, said second input being coupled to said output of said second flipflop, said output providing a data hold-time signal.
Claim 16
Dependent Claim
42 words
The parallel to serial converter circuit of claim 12 wherein said circuit means further includes an inverter having an input receiving said one bit of said data word and having an output for providing said inverted one bit of said data word.
Claim 17
Dependent Claim
33 words
The parallel to serial converter circuit of claim 13 further including a first logic level translator circuit having inputs receiving said data word and having outputs coupled to said inputs of said register.
Claim 18
Dependent Claim
51 words
The parallel to serial converter circuit of claim 14 further including a third flipflop having a data input, a clock input, and an output, said data input being coupled to said output of said multiplexer, said clock input being receiving a flipflop clock signal, said output providing a data output signal.
Claim 19
Dependent Claim
36 words
The parallel to serial converter circuit of claim 15 further including a logic circuit for generating said register clock signal, said flipflop clock signal, and said multiplexer control signal in response to a system clock signal.
References Cited (Backward Citations)
US5291141A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-20 | 2000-02-19 | 2000-08-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-20 | 2004-02-19 | 2004-08-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-20 | 2008-02-19 | 2008-08-20 | $7700.00 | Window Closed / Lapsed |