Flexible switching hub for a communication network

Claim 2

A communication subsystem comprising: a central processing unit (CPU); a communication segment comprising: a switched hub circuit comprising a plurality of serial communication ports, each serial communication port comprising: a transmit first-in-first-out buffer (FIFO); a receive FIFO; a transmit direct memory access (DMA) circuit; a receive DMA circuit; and a communication control circuit; a dynamic random access memory (DRAM) subsystem, the DRAM subsystem comprising a plurality of virtual transmit FIFOs (VTFs), each VTF corresponding to a serial communication port of the plurality of serial communication ports, each VTF comprising a plurality of frame buffers; and a system interconnect bus coupling the switched hub circuit, the DRAM subsystem and the CPU.

Claim 3

The communication subsystem of claim 1, wherein the switched hub circuit further comprises a control and arbitration circuit coupled to the plurality of serial communication ports, the control and arbitration circuit comprising a content addressable memory (CAM) comprising an address translation table containing destination port addresses of incoming communication frames.

Claim 4

The communication subsystem of claim 1, wherein the switched hub circuit further comprises a plurality of parallel communication ports, each parallel communication port comprising a transmit FIFO, a receive FIFO, a plurality of transmit DMA circuits, a plurality of receive DMA circuits, and a bus interface circuit.

Claim 5

The communication subsystem of claim 1, wherein the CPU analyzes frame buffer usage in the VTFs and allocates frame buffers among the VTFs accordingly, and wherein the VTF comprises flags indicating the state of VTF fame buffers, the flags being set or reset by the CPU according to the state of the VTF frame buffers.

Claim 6

The communication subsystem of claim 1, wherein the DRAM subsystem further comprises a broadcast memory structure which includes broadcast frame buffers and a free buffer list, the free buffer list being managed by the CPU.

Claim 7

A communication method comprising the steps of: (A) receiving a communication frame in a receive first-in-first-out buffer (FIFO) of a source port; (B) determining a destination port for the communication frame received; (C) transferring the communication frame received to a virtual transmit FIFO (VTF) corresponding to the destination port using a receive direct memory access (DMA) circuit, the communication frame being stored in frame buffers of the VTF in order of arrival with respect to communication frames from different source ports being sent to the destination port, the communication frame and the communication frames from different source ports being interleaved in the VTF; and (D) transferring a topmost frame buffer of the VTF to a transmit FIFO in the destination port using a transmit DMA circuit.

Claim 8

A communication method comprising the steps of: (A) receiving a communication frame in a receive first-in-first-out buffer (FIFO) of a source port; (B) determining a destination port for the communication frame received; (C) transferring the communication frame received to a virtual transmit FIFO (VTF) corresponding to the destination port using a receive direct memory access (DMA) circuit, the communication frame being stored in frame buffers of the VTF in order of arrival with respect to communication frames from different source ports being sent to the destination port, the communication frame and the communication frames from different source ports being interleaved in the VTF; and (D) transferring a topmost frame buffer of the VTF to a transmit FIFO in the destination port using a transmit DMA circuit.

Claim 9

The communication method of claim 6, wherein step (C) further comprises the steps of: using a destination address of the communication frame as an index to an address translation table in a content addressable memory (CAM); reading a destination pointer from the address translation table to identify the destination port; retrieving a pointer to a next free frame buffer in the VTF; and sending the communication frame to the VTF over a system interconnect bus interleaved with the communication frames from different source ports.

Claim 10

The communication method of claim 7, further comprising the steps of: setting an internal FIFO length (IFL) bit in a header of the VTF each time a block the size of the transmit FIFO is transferred to the VTF; setting a receive data transfer completed (RDTC) flag each time a receive operation on the communication frame is completed, setting a VTF -- full flag when there is no free frame buffer in the VTF and placing a header of the communication frame in a request queue of the VTF.

Claim 11

The communication method of claim 6, further comprising the step of: (E) executing a congestion control process on the CPU wherein statistics on VTF usage are gathered and allocation of frame buffers in the VTF are modified accordingly.

Claim 12

The communication method of claim 6, further comprising the steps of: (F) receiving a multicast communication frame having multiple destination ports and placing the multicast communication frame in a frame buffer of a broadcast memory structure; (G) writing a header to a corresponding VTF of each of the multiple destination ports; (H) inhibiting transfer of newly received communication frames to the corresponding VTFs until the headers are written the corresponding VTFs.

Claim 13

A communication system comprising: a plurality of communication agents; a communication subsystem coupled to the plurality of communication agents, the communication subsystem comprising: a plurality of central processing unit (CPU) subsystems; a plurality of communication segments, a communication segment comprising: a switched hub circuit comprising: a plurality of serial communication ports, each serial communication port comprising a transmit first in first out buffer (FIFO), a receive FIFO, a transmit direct memory access (DMA) circuit, and a receive DMA circuit; and a plurality of parallel communication ports, each parallel communication port comprising a transmit FIFO, a receive FIFO, a plurality of transmit DMAs, a plurality of receive DMAs, and a bus interface circuit; a dynamic random access memory (DRAM) subsystem comprising: a plurality of virtual transmit FIFOs (VTFs), each VTF corresponding to a serial communication port of the plurality of serial communication ports, each VTF comprising a plurality of frame buffers; a broadcast memory structure; and a control memory block; and a system interconnect bus coupling the plurality of CPU subsystems and the plurality of communication segments.

Claim 14

A communication system comprising: a plurality of communication agents; a communication subsystem coupled to the plurality of communication agents, the communication subsystem comprising: a plurality of central processing unit (CPU) subsystems; a plurality of communication segments, a communication segment comprising: a switched hub circuit comprising: a plurality of serial communication ports, each serial communication port comprising a transmit first in first out buffer (FIFO), a receive FIFO, a transmit direct memory access (DMA) circuit, and a receive DMA circuit; and a plurality of parallel communication ports, each parallel communication port comprising a transmit FIFO, a receive FIFO, a plurality of transmit DMAs, a plurality of receive DMAs, and a bus interface circuit; a dynamic random access memory (DRAM) subsystem comprising: a plurality of virtual transmit FIFOs (VTFs), each VTF corresponding to a serial communication port of the plurality of serial communication ports, each VTF comprising a plurality of frame buffers; a broadcast memory structure; and a control memory block; and a system interconnect bus coupling the plurality of CPU subsystems and the plurality of communication segments.

Claim 15

The communication system of claim 11, wherein the broadcast memory structure comprises broadcast frame buffers and a free buffer list, the free buffer list being managed by the CPU.

Claim 16

The communication system of claim 11, wherein the switched hub circuit further comprises a control and arbitration circuit comprising a content addressable memory (CAM), the CAM comprising an address translation table.