US5546042A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High precision voltage regulation circuit for programming multiple bit flash memory
Assignee: Intel Corp
•
Filing: 1995-04-17
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Granted: 1996-08-13
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Expires: 2015-04-17
Abstract
Abstract A voltage regulation circuit that includes a sample and hold circuit for sampling an input voltage and for holding a reference voltage generated in response to the input voltage. The sample and hold circuit includes a capacitor that holds the reference voltage. The voltage regulation circuit also includes a regulator circuit coupled to the capacitor of the sample and hold circuit. The regulator circuit outputs an output voltage using the reference voltage supplied by the capacitor. The voltage regulation circuit may be used to provide a high precision programming voltage for programming memory cells having two or more analog states.
Inventors
- 👤 Kerry D. Tedrow
- 👤 Stephen N. Keeney
- 👤 Albert Fazio
- 👤 Gregory E. Atwood
- 👤 Johnny Javanifard
- 👤 Kenneth Wojciechowski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 19:54
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/56; G11C11/5621; G05; G05F; G05F1/00; G05F1/10; G05F1/46; G05F1/462; G05F1/465; G11C16/00; G11C16/02; G11C16/06; G11C16/30; G11C5/00; G11C5/14; G11C5/147
Claims Analysis
Total Claims: 54
Claim 1
Independent Claim
147 words
A computer system comprising: a power supply for providing an operating voltage; a DC-to-DC converter coupled to receive the operating voltage, the DC-to-DC converter for outputting a programming voltage level; a nonvolatile memory device coupled to receive the programming voltage level, the nonvolatile memory device including a programming voltage regulation circuit for supplying a gate voltage to program a nonvolatile memory cell, the programming voltage regulation circuit comprising: a sample and hold circuit coupled to the programming voltage level, the sample and hold circuit for sampling the programming voltage level and for holding a reference voltage generated in response to the programming voltage level, the sample and hold circuit including a capacitor that holds the reference voltage; and a regulator circuit coupled to the capacitor of the sample and hold circuit, the regulator circuit for outputting the gate voltage using the reference voltage supplied by the capacitor.
Claim 2
Dependent Claim
147 words
A computer system comprising: a power supply for providing an operating voltage; a DC-to-DC converter coupled to receive the operating voltage, the DC-to-DC converter for outputting a programming voltage level; a nonvolatile memory device coupled to receive the programming voltage level, the nonvolatile memory device including a programming voltage regulation circuit for supplying a gate voltage to program a nonvolatile memory cell, the programming voltage regulation circuit comprising: a sample and hold circuit coupled to the programming voltage level, the sample and hold circuit for sampling the programming voltage level and for holding a reference voltage generated in response to the programming voltage level, the sample and hold circuit including a capacitor that holds the reference voltage; and a regulator circuit coupled to the capacitor of the sample and hold circuit, the regulator circuit for outputting the gate voltage using the reference voltage supplied by the capacitor.
Claim 3
Dependent Claim
18 words
The computer system of claim 1, wherein the external input voltage is supplied by a regulated power supply.
Claim 4
Dependent Claim
18 words
The computer system of claim 2, wherein the external input voltage is supplied by a static voltage reference.
Claim 5
Dependent Claim
102 words
The computer system of claim 1, wherein the sample and hold circuit further comprises: an input circuit coupled to the input voltage, the input circuit for generating the reference voltage in response to the input voltage; a switch coupled to the input circuit and the capacitor, the switch for coupling the input circuit to the capacitor in response to a first control signal when the first control signal is in a first state such that the capacitor is charged to the reference voltage and for decoupling the input circuit from the capacitor when the first control signal is in a second state.
Claim 6
Dependent Claim
48 words
The computer system of claim 4, wherein the input circuit comprises: a first resistor coupled to the external input voltage; a second resistor coupled in series with the first resistor to system ground, wherein the reference voltage is supplied at a node between the first and second resistors.
Claim 7
Dependent Claim
38 words
The computer system of claim 5, wherein the input circuit further comprises: a precharge circuit coupled to the node between the first and second resistors and to a supply voltage, the precharge circuit for quickly charging the capacitor.
Claim 8
Dependent Claim
23 words
The computer system of claim 6, wherein the first resistor is coupled to the supply voltage in response to a second control signal.
Claim 9
Dependent Claim
23 words
The computer system of claim 7, wherein the precharge circuit is coupled to the supply voltage in response to a third control signal.
Claim 10
Dependent Claim
16 words
The computer system of claim 5, wherein the input voltage is equivalent to the supply voltage.
Claim 11
Dependent Claim
87 words
The computer system of claim 1, wherein the regulator circuit comprises: an operational amplifier having an output, a positive input and a negative input, wherein the positive input is coupled to receive the reference voltage; a programmable resistive divider circuit coupled to the output of the operational amplifier, the programmable resistive divider circuit for providing the output voltage in response to the output of the operational amplifier and a control signal, wherein the negative input of the operational amplifier is coupled to the programmable resistive divider circuit.
Claim 12
Dependent Claim
25 words
The computer system of claim 10, wherein the operational amplifier includes a p-channel field effect transistor having a gate, the gate being the positive input.
Claim 13
Dependent Claim
22 words
The computer system of claim 10, wherein a first capacitance of the capacitor is greater than a capacitance for the operational amplifier.
Claim 14
Dependent Claim
53 words
The computer system of claim 10, wherein the programmable resistive divider circuit comprises: a plurality of resistors coupled in series between the output of the operational amplifier and system ground; and a selector circuit coupled to the plurality of resistors, the selector circuit for selecting a tap point in the plurality of resistors.
Claim 15
Dependent Claim
32 words
The computer system of claim 1, wherein the DC-to-DC converter comprises a plurality of supply pins, each of the supply pins being isolated from other supply pins such that noise is reduced.
Claim 16
Dependent Claim
30 words
The computer system of claim 1, wherein the programming voltage regulation circuit supplies a drain voltage to a drain of the nonvolatile memory cell to program the nonvolatile memory cell.
Claim 17
Dependent Claim
30 words
The computer system of claim 1, wherein the programming voltage regulation circuit supplies a source voltage to a source of the nonvolatile memory cell to program the nonvolatile memory cell.
Claim 18
Dependent Claim
18 words
The computer system of claim 1, wherein the nonvolatile memory cell can achieve at least three analog states.
Claim 19
Dependent Claim
168 words
A computer system comprising: a power supply for providing an operating voltage; a solid state hard drive for storing data and for emulating a magnetic hard disk drive, the solid state hard drive comprising: a DC-to-DC converter coupled to receive the operating voltage, the DC-to-DC converter for outputting a programming voltage level; a nonvolatile memory device coupled to receive the programming voltage level, the nonvolatile memory device including a programming voltage regulation circuit for supplying a gate voltage to program a nonvolatile memory cell, the programming voltage regulation circuit comprising: a sample and hold circuit coupled to programming voltage level, the sample and hold circuit for sampling the programming voltage level and for holding a reference voltage generated in response to the programming voltage level, the sample and hold circuit including a capacitor that holds the reference voltage; and a regulator circuit coupled to the capacitor of the sample and hold circuit, the regulator circuit for outputting the gate voltage using the reference voltage supplied by the capacitor.
Claim 20
Dependent Claim
168 words
A computer system comprising: a power supply for providing an operating voltage; a solid state hard drive for storing data and for emulating a magnetic hard disk drive, the solid state hard drive comprising: a DC-to-DC converter coupled to receive the operating voltage, the DC-to-DC converter for outputting a programming voltage level; a nonvolatile memory device coupled to receive the programming voltage level, the nonvolatile memory device including a programming voltage regulation circuit for supplying a gate voltage to program a nonvolatile memory cell, the programming voltage regulation circuit comprising: a sample and hold circuit coupled to programming voltage level, the sample and hold circuit for sampling the programming voltage level and for holding a reference voltage generated in response to the programming voltage level, the sample and hold circuit including a capacitor that holds the reference voltage; and a regulator circuit coupled to the capacitor of the sample and hold circuit, the regulator circuit for outputting the gate voltage using the reference voltage supplied by the capacitor.
Claim 21
Dependent Claim
18 words
The computer system of claim 18, wherein the external input voltage is supplied by a regulated power supply.
Claim 22
Dependent Claim
18 words
The computer system of claim 19, wherein the external input voltage is supplied by a static voltage reference.
Claim 23
Dependent Claim
102 words
The computer system of claim 18, wherein the sample and hold circuit further comprises: an input circuit coupled to the input voltage, the input circuit for generating the reference voltage in response to the input voltage; a switch coupled to the input circuit and the capacitor, the switch for coupling the input circuit to the capacitor in response to a first control signal when the first control signal is in a first state such that the capacitor is charged to the reference voltage and for decoupling the input circuit from the capacitor when the first control signal is in a second state.
Claim 24
Dependent Claim
48 words
The computer system of claim 21, wherein the input circuit comprises: a first resistor coupled to the external input voltage; a second resistor coupled in series with the first resistor to system ground, wherein the reference voltage is supplied at a node between the first and second resistors.
Claim 25
Dependent Claim
38 words
The computer system of claim 22, wherein the input circuit further comprises: a precharge circuit coupled to the node between the first and second resistors and to a supply voltage, the precharge circuit for quickly charging the capacitor.
Claim 26
Dependent Claim
23 words
The computer system of claim 23, wherein the first resistor is coupled to the supply voltage in response to a second control signal.
Claim 27
Dependent Claim
23 words
The computer system of claim 24, wherein the precharge circuit is coupled to the supply voltage in response to a third control signal.
Claim 28
Dependent Claim
16 words
The computer system of claim 22, wherein the input voltage is equivalent to the supply voltage.
Claim 29
Dependent Claim
87 words
The computer system of claim 18, wherein the regulator circuit comprises: an operational amplifier having an output, a positive input and a negative input, wherein the positive input is coupled to receive the reference voltage; a programmable resistive divider circuit coupled to the output of the operational amplifier, the programmable resistive divider circuit for providing the output voltage in response to the output of the operational amplifier and a control signal, wherein the negative input of the operational amplifier is coupled to the programmable resistive divider circuit.
Claim 30
Dependent Claim
25 words
The computer system of claim 27, wherein the operational amplifier includes a p-channel field effect transistor having a gate, the gate being the positive input.
Claim 31
Dependent Claim
22 words
The computer system of claim 27, wherein a first capacitance of the capacitor is greater than a capacitance for the operational amplifier.
Claim 32
Dependent Claim
53 words
The computer system of claim 27, wherein the programmable resistive divider circuit comprises: a plurality of resistors coupled in series between the output of the operational amplifier and system ground; and a selector circuit coupled to the plurality of resistors, the selector circuit for selecting a tap point in the plurality of resistors.
Claim 33
Dependent Claim
32 words
The computer system of claim 18, wherein the DC-to-DC converter comprises a plurality of supply pins, each of the supply pins being isolated from other supply pins such that noise is reduced.
Claim 34
Dependent Claim
30 words
The computer system of claim 18, wherein the programming voltage regulation circuit supplies a drain voltage to a drain of the nonvolatile memory cell to program the nonvolatile memory cell.
Claim 35
Dependent Claim
30 words
The computer system of claim 18, wherein the programming voltage regulation circuit supplies a source voltage to a source of the nonvolatile memory cell to program the nonvolatile memory cell.
Claim 36
Dependent Claim
18 words
The computer system of claim 18, wherein the nonvolatile memory cell can achieve at least three analog states.
Claim 37
Dependent Claim
156 words
A computer system comprising: a power supply for providing an operating voltage; a memory card for storing data, the memory card comprising: a DC-to-DC converter coupled to receive the operating voltage, the DC-to-DC converter for outputting a programming voltage level; a nonvolatile memory device coupled to receive the programming voltage level, the nonvolatile memory device including a programming voltage regulation circuit for supplying a gate voltage to program a nonvolatile memory cell, the programming voltage regulation circuit comprising: a sample and hold circuit coupled to programming voltage level the sample and hold circuit for sampling the programming voltage level, and for holding a reference voltage generated in response to the programming voltage level, the sample and hold circuit including a capacitor that holds the reference voltage; and a regulator circuit coupled to the capacitor of the sample and hold circuit, the regulator circuit for outputting the gate voltage using the reference voltage supplied by the capacitor.
Claim 38
Dependent Claim
156 words
A computer system comprising: a power supply for providing an operating voltage; a memory card for storing data, the memory card comprising: a DC-to-DC converter coupled to receive the operating voltage, the DC-to-DC converter for outputting a programming voltage level; a nonvolatile memory device coupled to receive the programming voltage level, the nonvolatile memory device including a programming voltage regulation circuit for supplying a gate voltage to program a nonvolatile memory cell, the programming voltage regulation circuit comprising: a sample and hold circuit coupled to programming voltage level the sample and hold circuit for sampling the programming voltage level, and for holding a reference voltage generated in response to the programming voltage level, the sample and hold circuit including a capacitor that holds the reference voltage; and a regulator circuit coupled to the capacitor of the sample and hold circuit, the regulator circuit for outputting the gate voltage using the reference voltage supplied by the capacitor.
Claim 39
Dependent Claim
18 words
The computer system of claim 35, wherein the external input voltage is supplied by a regulated power supply.
Claim 40
Dependent Claim
18 words
The computer system of claim 36, wherein the external input voltage is supplied by a static voltage reference.
Claim 41
Dependent Claim
102 words
The computer system of claim 35, wherein the sample and hold circuit further comprises: an input circuit coupled to the input voltage, the input circuit for generating the reference voltage in response to the input voltage; a switch coupled to the input circuit and the capacitor, the switch for coupling the input circuit to the capacitor in response to a first control signal when the first control signal is in a first state such that the capacitor is charged to the reference voltage and for decoupling the input circuit from the capacitor when the first control signal is in a second state.
Claim 42
Dependent Claim
48 words
The computer system of claim 38, wherein the input circuit comprises: a first resistor coupled to the external input voltage; a second resistor coupled in series with the first resistor to system ground, wherein the reference voltage is supplied at a node between the first and second resistors.
Claim 43
Dependent Claim
38 words
The computer system of claim 39, wherein the input circuit further comprises: a precharge circuit coupled to the node between the first and second resistors and to a supply voltage, the precharge circuit for quickly charging the capacitor.
Claim 44
Dependent Claim
23 words
The computer system of claim 40, wherein the first resistor is coupled to the supply voltage in response to a second control signal.
Claim 45
Dependent Claim
23 words
The computer system of claim 41, wherein the precharge circuit is coupled to the supply voltage in response to a third control signal.
Claim 46
Dependent Claim
16 words
The computer system of claim 39, wherein the input voltage is equivalent to the supply voltage.
Claim 47
Dependent Claim
87 words
The computer system of claim 35, wherein the regulator circuit comprises: an operational amplifier having an output, a positive input and a negative input, wherein the positive input is coupled to receive the reference voltage; a programmable resistive divider circuit coupled to the output of the operational amplifier, the programmable resistive divider circuit for providing the output voltage in response to the output of the operational amplifier and a control signal, wherein the negative input of the operational amplifier is coupled to the programmable resistive divider circuit.
Claim 48
Dependent Claim
25 words
The computer system of claim 44, wherein the operational amplifier includes a p-channel field effect transistor having a gate, the gate being the positive input.
Claim 49
Dependent Claim
22 words
The computer system of claim 44, wherein a first capacitance of the capacitor is greater than a capacitance for the operational amplifier.
Claim 50
Dependent Claim
53 words
The computer system of claim 44, wherein the programmable resistive divider circuit comprises: a plurality of resistors coupled in series between the output of the operational amplifier and system ground; and a selector circuit coupled to the plurality of resistors, the selector circuit for selecting a tap point in the plurality of resistors.
Claim 51
Dependent Claim
32 words
The computer system of claim 35, wherein the DC-to-DC converter comprises a plurality of supply pins, each of the supply pins being isolated from other supply pins such that noise is reduced.
Claim 52
Dependent Claim
30 words
The computer system of claim 35, wherein the programming voltage regulation circuit supplies a drain voltage to a drain of the nonvolatile memory cell to program the nonvolatile memory cell.
Claim 53
Dependent Claim
30 words
The computer system of claim 35, wherein the programming voltage regulation circuit supplies a source voltage to a source of the nonvolatile memory cell to program the nonvolatile memory cell.
Claim 54
Dependent Claim
18 words
The computer system of claim 35, wherein the nonvolatile memory cell can achieve at least three analog states.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-13 | 2000-02-12 | 2000-08-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-13 | 2004-02-12 | 2004-08-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-13 | 2008-02-12 | 2008-08-13 | $7700.00 | Window Closed / Lapsed |