US5546022A
Expired / Lapsed
US
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Static logic circuit with improved output signal levels
Assignee: Sun Microsystems Inc
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Filing: 1994-12-16
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Granted: 1996-08-13
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Expires: 2014-12-16
Abstract
Abstract A static logic circuit with improved output signal levels includes a static complementary MOSFET circuit with a signal node and pull-up and pull-down amplifiers, each with at least one biasing circuit, connected thereto. The pull-up and pull-down amplifiers are connected to VDD and VSS, respectively, and receive one or more logic signals (e.g. one for an inverter and more for logic gates such as AND, OR, etc.) and one or more bias signals and in accordance therewith provide pull-up and pull-down voltages, respectively, to the signal node. In accordance with the applied pull-up or pull-down voltage, the signal node charges to a charge state with an associated node voltage approximately equal to VDD or VSS, respectively. Each biasing circuit receives the same input logic signal as its associated pull-up or pull-down amplifier and provides thereto a bias signal approximately equal to VSS or VDD, respectively. In accordance with its input logic signal, each pull-up or pull-down amplifier together with its associated biasing circuit provides either an active current path between the signal node and VDD or VSS for applying the desired pull-up or pull-down voltage, respectively, or a leakage current path between VDD and VSS for preventing the application of an undesired pull-down or pull-up voltage during application of the desired pull-up or pull-down voltage, respectively.
Inventors
- 👤 Godfrey P. D'Souza
- 👤 Douglas A. Laird
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 11:36
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/20; H03K19/003; H03K19/00346; H03K19/00361
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
148 words
An apparatus including a low powered static logic circuit with improved output signal levels, said low powered static logic circuit comprising: a first supply node for operating at a first voltage level; a second supply node for operating at a second voltage level; an output signal node intermediate said first and second supply nodes; a first input circuit, coupled between said output signal node and said first supply node, for receiving a first input signal and in response thereto coupling said output signal node to said first supply node at said first voltage level; and a first bias circuit, coupled between said output signal node and said second supply node, for receiving said first input signal and in response thereto substantially maintaining said first voltage level at said output signal node when said output signal node is coupled to said first supply node by said first input circuit.
Claim 2
Independent Claim
148 words
An apparatus including a low powered static logic circuit with improved output signal levels, said low powered static logic circuit comprising: a first supply node for operating at a first voltage level; a second supply node for operating at a second voltage level; an output signal node intermediate said first and second supply nodes; a first input circuit, coupled between said output signal node and said first supply node, for receiving a first input signal and in response thereto coupling said output signal node to said first supply node at said first voltage level; and a first bias circuit, coupled between said output signal node and said second supply node, for receiving said first input signal and in response thereto substantially maintaining said first voltage level at said output signal node when said output signal node is coupled to said first supply node by said first input circuit.
Claim 3
Dependent Claim
34 words
An apparatus as recited in claim 1, wherein said first bias circuit substantially reduces current flow through said first input circuit when said output signal node is coupled thereby to said first supply node.
Claim 4
Dependent Claim
32 words
An apparatus as recited in claim 1, wherein said first input circuit comprises a first transistor for pulling said output signal node to said first supply node at said first voltage level.
Claim 5
Dependent Claim
76 words
An apparatus as recited in claim 3, wherein said first bias circuit comprises a second transistor coupled to an intermediate node which is intermediate said output signal node and said second supply node for pulling said intermediate node toward said first voltage level and thereby substantially reducing current flow between said output signal node and said second supply node when said output signal node is coupled to said first supply node by said first input circuit.
Claim 6
Dependent Claim
28 words
An apparatus as recited in claim 4, wherein said first transistor is a pull-up transistor, said first voltage level is VDD and said second voltage level is VSS.
Claim 7
Dependent Claim
28 words
An apparatus as recited in claim 4, wherein said first transistor is a pull-down transistor, said first voltage level is VSS and said second voltage level is VDD.
Claim 8
Dependent Claim
16 words
An apparatus as recited in claim 4, wherein said first and second transistors are P-MOS transistors.
Claim 9
Dependent Claim
16 words
An apparatus as recited in claim 4, wherein said first and second transistors are N-MOS transistors.
Claim 10
Dependent Claim
94 words
An apparatus as recited in claim 1, further comprising: a second input circuit, coupled between said output signal node and said second supply node, for receiving a second input signal and in response thereto coupling said output signal node to said second supply node at said second voltage level; and a second bias circuit, coupled between said output signal node and said first supply node, for substantially maintaining said second voltage level at said output signal node when said output signal node is coupled to said second supply node by said second input circuit.
Claim 11
Dependent Claim
34 words
An apparatus as recited in claim 9, wherein said second bias circuit substantially reduces current flow through said second input circuit when said output signal node is coupled thereby to said second supply node.
Claim 12
Dependent Claim
24 words
An apparatus as recited in claim 1, wherein said first input circuit and said first bias circuit together include a plurality of MOS transistors.
Claim 13
Dependent Claim
29 words
An apparatus as recited in claim 1, wherein said low powered static logic circuit implements one of the following logic function: inversion; AND; OR; NAND; NOR; EXOR; and EXNOR.
Claim 14
Dependent Claim
22 words
An apparatus as recited in claim 1, further comprising an integrated circuit into which said low powered static logic circuit is integrated.
Claim 15
Dependent Claim
21 words
An apparatus as recited in claim 1, further comprising a computer into which said low powered static logic circuit is incorporated.
Claim 16
Independent Claim
156 words
A method of providing an apparatus including a low powered static logic circuit with improved output signal levels, said method comprising the steps of: providing a first supply node for operating at a first voltage level; providing a second supply node for operating at a second voltage level; providing an output signal node intermediate said first and second supply nodes; providing a first input circuit, coupled between said output signal node and said first supply node, for receiving a first input signal and in response thereto coupling said output signal node to said first supply node at said first voltage level; and providing a first bias circuit, coupled between said output signal node and said second supply node, for receiving said first input signal and in response thereto substantially maintaining said first voltage level at said output signal node when said output signal node is coupled to said first supply node by said first input circuit.
Claim 17
Independent Claim
156 words
A method of providing an apparatus including a low powered static logic circuit with improved output signal levels, said method comprising the steps of: providing a first supply node for operating at a first voltage level; providing a second supply node for operating at a second voltage level; providing an output signal node intermediate said first and second supply nodes; providing a first input circuit, coupled between said output signal node and said first supply node, for receiving a first input signal and in response thereto coupling said output signal node to said first supply node at said first voltage level; and providing a first bias circuit, coupled between said output signal node and said second supply node, for receiving said first input signal and in response thereto substantially maintaining said first voltage level at said output signal node when said output signal node is coupled to said first supply node by said first input circuit.
Claim 18
Dependent Claim
34 words
A method as recited in claim 15, wherein said first bias circuit substantially reduces current flow through said first input circuit when said output signal node is coupled thereby to said first supply node.
Claim 19
Dependent Claim
99 words
A method as recited in claim 15, further comprising the steps of: providing a second input circuit, coupled between said output signal node and said second supply node, for receiving a second input signal and in response thereto coupling said output signal node to said second supply node at said second voltage level; and providing a second bias circuit, coupled between said output signal node and said first supply node, for substantially maintaining said second voltage level at said output signal node when said output signal node is coupled to said second supply node by said second input circuit.
Claim 20
Dependent Claim
34 words
A method as recited in claim 17, wherein said second bias circuit substantially reduces current flow through said second input circuit when said output signal node is coupled thereby to said second supply node.
Claim 21
Dependent Claim
26 words
A method as recited in claim 15, further comprising the step of providing an integrated circuit into which said low powered static logic circuit is integrated.
Claim 22
Dependent Claim
25 words
A method as recited in claim 15, further comprising the step of providing a computer into which said low powered static logic circuit is incorporated.
Claim 23
Independent Claim
131 words
A method of statically, logically processing logic signals with improved output signal levels at low power, said method comprising the steps of: operating a first supply node at a first voltage level; operating a second supply node at a second voltage level; receiving a first input signal and in response thereto coupling an output signal node which is intermediate said first and second supply nodes to said first supply node at said first voltage level; and receiving said first input signal and in response thereto applying a first bias between said output signal node and said second supply node and thereby substantially maintaining said first voltage level at said output signal node when said output signal node is coupled to said first supply node in response to said first input signal.
Claim 24
Independent Claim
131 words
A method of statically, logically processing logic signals with improved output signal levels at low power, said method comprising the steps of: operating a first supply node at a first voltage level; operating a second supply node at a second voltage level; receiving a first input signal and in response thereto coupling an output signal node which is intermediate said first and second supply nodes to said first supply node at said first voltage level; and receiving said first input signal and in response thereto applying a first bias between said output signal node and said second supply node and thereby substantially maintaining said first voltage level at said output signal node when said output signal node is coupled to said first supply node in response to said first input signal.
Claim 25
Dependent Claim
100 words
A method as recited in claim 21, wherein said step of receiving said first input signal and in response thereto applying a first bias between said output signal node and said second supply node and thereby substantially maintaining said first voltage level at said output signal node when said output signal node is coupled to said first supply node in response to said first input signal comprises substantially reducing current flow from said output signal node to said second supply node when said output signal node is coupled to said first supply node in response to said first input signal.
Claim 26
Dependent Claim
83 words
A method as recited in claim 21, further comprising the steps of: receiving a second input signal and in response thereto coupling said output signal node to said second supply node at said second voltage level; and applying a second bias between said output signal node and said first supply node and thereby substantially maintaining said second voltage level at said output signal node when said output signal node is coupled to said second supply node in response to said second input signal.
Claim 27
Dependent Claim
91 words
A method as recited in claim 23, wherein said step of applying a second bias between said output signal node and said first supply node and thereby substantially maintaining said second voltage level at said output signal node when said output signal node is coupled to said second supply node in response to said second input signal comprises substantially reducing current flow from said output signal node to said first supply node when said output signal node is coupled to said second supply node in response to said second input signal.
Claim 28
Dependent Claim
20 words
A method as recited in claim 21, further comprising the step of performing the recited steps within an integrated circuit.
Claim 29
Dependent Claim
19 words
A method as recited in claim 21, further comprising the step of performing the recited steps within a computer.
Claim 30
Independent Claim
179 words
An apparatus including a low powered static logic circuit with improved output signal levels, said low powered static logic circuit comprising: a first supply node for operating at a first voltage level; a second supply node for operating at a second voltage level; an output signal node intermediate said first and second supply nodes; a first input circuit, coupled between said output signal node and said first supply node, for receiving a first input signal and in response thereto coupling said output signal node to said first supply node at said first voltage level; and a first bias circuit, coupled between said output signal node and said second supply node, for substantially maintaining said first voltage level at said output signal node when said output signal node is coupled to said first supply node by said first input circuit; wherein said first input circuit and said first bias circuit together include a plurality of MOS transistors, and wherein each one of said plurality of MOS transistors is for operating at a poewr supply voltage of less than 3.5 volts.
Claim 31
Independent Claim
179 words
An apparatus including a low powered static logic circuit with improved output signal levels, said low powered static logic circuit comprising: a first supply node for operating at a first voltage level; a second supply node for operating at a second voltage level; an output signal node intermediate said first and second supply nodes; a first input circuit, coupled between said output signal node and said first supply node, for receiving a first input signal and in response thereto coupling said output signal node to said first supply node at said first voltage level; and a first bias circuit, coupled between said output signal node and said second supply node, for substantially maintaining said first voltage level at said output signal node when said output signal node is coupled to said first supply node by said first input circuit; wherein said first input circuit and said first bias circuit together include a plurality of MOS transistors, and wherein each one of said plurality of MOS transistors is for operating at a poewr supply voltage of less than 3.5 volts.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-13 | 2000-02-12 | 2000-08-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-13 | 2004-02-12 | 2004-08-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-13 | 2008-02-12 | 2008-08-13 | $7700.00 | Window Closed / Lapsed |