US5543979A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Preamplifier circuit arrangements for common current flow in a transducer
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1994-09-08
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Granted: 1996-08-06
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Expires: 2014-09-08
Abstract
Abstract A preamplifier circuit arrangement for a magnetic or magneto resistive transducer, such as a record/replay head, in which a cascode preamplifier stage, and a stage providing a floating reference voltage for a following amplifier, are linked by an emitter coupled pair of transistors, one in each stage, such that the d.c. currents in the two stages flow in common through the transducer.
Inventors
- 👤 Richard Davies
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 20:46
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/72; H03F1/00; H03F1/08; H03F1/22; G; G11; G11B; G11B19/00; G11B19/02; G11B5/00; G11B2005/0002; G11B2005/0005; G11B2005/001; G11B2005/0013; G11B2005/0016; G11B2005/0018; G11B33/00; G11B33/14
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
109 words
A preamplifier circuit arrangement for a magnetic or magnetoresistive transducer or record and replay head, comprising; an emitter-coupled pair of transistors having respective constant current sources in their collector circuits and bias circuit means to apply d.c. biases to their respective bases, means to connect said transducer or record and replay head between said emitter-coupled pair of transistors and a point of ground potential, means to connect one of said pair of transistors in common base mode to alternating signal currents flowing in said transducer or record and replay head, and means to derive alternating output signals from the collector circuit of said one of said pair of transistors.
Claim 2
Dependent Claim
109 words
A preamplifier circuit arrangement for a magnetic or magnetoresistive transducer or record and replay head, comprising; an emitter-coupled pair of transistors having respective constant current sources in their collector circuits and bias circuit means to apply d.c. biases to their respective bases, means to connect said transducer or record and replay head between said emitter-coupled pair of transistors and a point of ground potential, means to connect one of said pair of transistors in common base mode to alternating signal currents flowing in said transducer or record and replay head, and means to derive alternating output signals from the collector circuit of said one of said pair of transistors.
Claim 3
Dependent Claim
124 words
A preamplifier circuit arrangement for any selected one of a plurality of magnetic or magnetoresistive transducers or record and replay heads, comprising: an emitter-coupled pair of transistors having respective construct current sources in their collector circuits and bias circuit means to apply d.c. biases to their respective bases, respective switching means selectively to connect any one of said transducers or record and replay heads between said emitter-coupled pair of transistors and a point of ground potential, means to connect one of said pair of transistors in common base mode to alternating signal currents flowing in said one of said transducers or record and replay heads, and means to derive alternating output signals from the collector circuit of said one of said pair of transistors.
Claim 4
Dependent Claim
124 words
A preamplifier circuit arrangement for any selected one of a plurality of magnetic or magnetoresistive transducers or record and replay heads, comprising: an emitter-coupled pair of transistors having respective construct current sources in their collector circuits and bias circuit means to apply d.c. biases to their respective bases, respective switching means selectively to connect any one of said transducers or record and replay heads between said emitter-coupled pair of transistors and a point of ground potential, means to connect one of said pair of transistors in common base mode to alternating signal currents flowing in said one of said transducers or record and replay heads, and means to derive alternating output signals from the collector circuit of said one of said pair of transistors.
Claim 5
Dependent Claim
33 words
A preamplifier circuit in accordance with claim 2 wherein said switching means comprises a respective switching transistor connected between said emitter coupled emitters and each of said transducers or record and replay heads.
Claim 6
Dependent Claim
30 words
A preamplifier circuit in accordance with claim 1, wherein the collector circuits of said embitter-coupled pair of transistors are coupled to respective inputs of an amplifier providing differential output signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-06 | 2000-02-05 | 2000-08-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-06 | 2004-02-05 | 2004-08-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-06 | 2008-02-05 | 2008-08-06 | $7700.00 | Window Closed / Lapsed |