Reset circuit for generating reset pulse over an interval of reduced voltage supply

Claim 2

A reset circuit comprising: (a) first means for providing a reset pulse, (b) second means connected to the first means for enabling said first means to stag said reset pulse, (c) third means connected to the second means for detecting a voltage drop of an initial supply voltage below a threshold and for enabling said second means in response to said detection, (d) means for extending a length of the reset pulse until a time of restoration of a full initial supply voltage (e) said third means comprising a first transistor in series with a first resistor between a source of said initial supply voltage and ground, (f) means connected to the first transistor for charging a capacitor through the first transistor from said voltage supply, (g) means connected to the first transistor for causing the first transistor to conduct in response to a on the first capacitor, (h) means connected to the first transistor and to the second means for inhibiting said second mean, and (i) means connected to the first transistor and to the second means for inhibiting conduction of the first transistor and for enabling said second means as a result thereof upon said supply voltage dropping below the voltage of the charge on the capacitor.

Claim 3

The reset circuit as defined in claim 1 in which said second means comprises a second transistor connected in a circuit to the first transistor and being inoperative in the presence of conduction by the first transistor, a second capacitor connected to the second transistor and charged by the supply voltage, and means connected to the second capacitor for discharging the second capacitor through the second transistor upon operation and conduction of the second transistor thereby enabling said first means.

Claim 4

The reset circuit as defined in claim 2 further including a variable resistor connected between the second capacitor and the supply voltage for controlling the charge time of the second capacitor and length of the reset pulse.

Claim 5

The reset circuit as defined in claim 3 in which said first means comprises an operational amplifier having a non-inverting input connected to the second capacitor and an inverting input connected to a voltage source, and means for providing the reset pulse from the output of the operational amplifier.

Claim 6

A reset circuit comprising: (a) an operational amplifier having an inverting input and a noninverting input, and an output for providing a reset pulse, (b) means for providing a first threshold voltage connected to an inverting input of the operational amplifier, (c) a first bipolar transistor having its emitter connected to a first pole of a supply voltage and its base connected through a first capacitor and first resistor to another pole of the supply voltage, (d) a second bipolar transistor having its base connected in a circuit to said other pole of the supply voltage and its emitter connected through a second resistor to a second capacitor, another terminal of the second capacitor being connected to said other pole of the supply voltage, (e) the junction of the second capacitor and the second resistor being connected through a third resistor to the first pole of the supply voltage and to the noninverting input of the operational amplifier, and (f) means for causing the second transistor to be nonconductive with conduction and operation of the first transistor, and for causing the second transistor to be conductive and discharge the second capacitor to a voltage less than the first threshold voltage applied to the inverting input of the operational amplifier upon nonconduction of the first transistor whereby a reset pulse is initiated by the operational amplifier.

Claim 7

A reset circuit comprising: (a) an operational amplifier having an inverting input and a noninverting input, and an output for providing a reset pulse, (b) means for providing a first threshold voltage connected to an inverting input of the operational amplifier, (c) a first bipolar transistor having its emitter connected to a first pole of a supply voltage and its base connected through a first capacitor and first resistor to another pole of the supply voltage, (d) a second bipolar transistor having its base connected in a circuit to said other pole of the supply voltage and its emitter connected through a second resistor to a second capacitor, another terminal of the second capacitor being connected to said other pole of the supply voltage, (e) the junction of the second capacitor and the second resistor being connected through a third resistor to the first pole of the supply voltage and to the noninverting input of the operational amplifier, and (f) means for causing the second transistor to be nonconductive with conduction and operation of the first transistor, and for causing the second transistor to be conductive and discharge the second capacitor to a voltage less than the first threshold voltage applied to the inverting input of the operational amplifier upon nonconduction of the first transistor whereby a reset pulse is initiated by the operational amplifier.

Claim 8

The reset circuit as defined in claim 5 in which the time constant of the first capacitor and first resistor is of the order of microseconds.

Claim 9

The reset circuit as defined in claim 5 in which the time constant of the second capacitor and second resistor is of the order of microseconds.

Claim 10

The reset circuit as defined in claim 5 in which the time constant of the second capacitor and third resistor is between about 1/2 second and 2 seconds.

Claim 11

The reset circuit as defined in claim 5 in which the third resistor is variable.

Claim 12

The reset circuit as defined in claim 5 in which the first pole of the supply voltage is positive and the transistors are PNP types.

Claim 13

The reset circuit as defined in claim 1 in which the first means comprises an operational amplifier having a threshold voltage applied to its inverting input, and a noninverting input connected to said voltage supply which is higher than the threshold voltage, the second means including a switch for switching the noninverting input of the operational amplifier to a voltage lower than the threshold voltage upon being enabled by said third means.

Claim 14

The reset circuit as defined in claim 11 in which the second means comprises a first capacitor in series with a discharge path, connected to the noninverting input of the operational amplifier, the discharge path being inhibited from conducting prior to the second means being enabled, and being enabled to conduct and discharge the first capacitor to ground, thereby bringing the noninverting input of the operational amplifier to ground.

Claim 15

The reset circuit as defined in claim 12 in which the third means comprises a capacitor charged to a voltage at or near the voltage of the voltage supply, and a conductive means which is inhibited from conducting upon the voltage supply becoming less than the voltage of the charge held by the capacitor, cessation of conduction of the conductive means triggering enabling of the second means to switch the noninverting input of the operational amplifier to a voltage lower than the threshold voltage.

Claim 16

The reset circuit as defined in claim 12 including a charge resistor in series with the first capacitor to the voltage supply, the charge resistor charging up the first capacitor to form a terminating edge of the reset pulse upon reestablishing initial voltage of the voltage supply following its detected drop with a time constant that delays the termination of the reset pulse to a predetermined extent.