US5543640A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logical three dimensional interconnections between integrated circuit chips using a two dimensional multi-chip module
Assignee: National Semiconductor Corp
•
Filing: 1995-09-29
•
Granted: 1996-08-06
•
Expires: 2015-09-29
Abstract
Abstract A high capacity gate array which incorporates an effectively three dimensional interconnect network. The array is formed from multiple smaller arrays which are connected to a common substrate by means of flip-chip bonding. The substrate is typically a multi-layer substrate which has interconnect lines embedded on or within it, thereby allowing a set of desired interconnections between the smaller logic cell arrays to be implemented. The contact points for connecting logic cells or arrays of cells to the substrate result from placing a multitude of solder bumps on the smaller arrays of logic cells at desired interconnect points. Connecting the interconnect point solder bumps to the multi-layer substrate then permits the individual logic cell arrays to be interconnected in a desired manner. A three dimensional interconnect network is realized by interconnecting corresponding points on different logic cell arrays so that the arrays are connected in parallel. This has the effect of producing a three dimensional interconnect network from a two dimensional arrangement of arrays or chips in a MCM package. The result is a high gate capacity logic device having an increased degree of gate utilization and shortened average interconnect distances, thereby enabling the production of complex devices which have a faster operating speed.
Inventors
- 👤 James Sutherland
- 👤 Timothy L. Garverick
- 👤 Hem P. Takiar
- 👤 George F. Reyling, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 11:09
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17736; H03K19/1778; H03K19/17796; H10; H10D; H10D89/00; H10D89/10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W70/62; H10W70/65; H10W90/00; H10W90/401
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
187 words
A three dimensionally extendible semiconductor based system, comprising: a substrate having bonding pads for mounting a plurality of lower functional capacity elements, the bonding pads serving to electrically connect the lower functional capacity elements to the substrate and to each other through an interconnect network on or within the substrate, wherein the interconnect network electrically connects a contact point on a first lower functional capacity element to a corresponding contact point on a second lower functional capacity element; and a plurality of lower functional capacity elements mounted on the substrate to combine said elements into a higher functional capacity element, the lower functional capacity elements including a plurality of logic gates and having a three dimensionally extendible architecture and being adapted to allow mounting and interconnection thereof to the substrate by the inclusion of a plurality of bonding contact points placed on the lower functional capacity elements, the bonding contact points being evenly distributed over the surface of the lower functional capacity elements, whereby a high functional capacity element having a high degree of logic gate utilization and shortened average interconnect distances and propagation delays is produced.
Claim 2
Dependent Claim
187 words
A three dimensionally extendible semiconductor based system, comprising: a substrate having bonding pads for mounting a plurality of lower functional capacity elements, the bonding pads serving to electrically connect the lower functional capacity elements to the substrate and to each other through an interconnect network on or within the substrate, wherein the interconnect network electrically connects a contact point on a first lower functional capacity element to a corresponding contact point on a second lower functional capacity element; and a plurality of lower functional capacity elements mounted on the substrate to combine said elements into a higher functional capacity element, the lower functional capacity elements including a plurality of logic gates and having a three dimensionally extendible architecture and being adapted to allow mounting and interconnection thereof to the substrate by the inclusion of a plurality of bonding contact points placed on the lower functional capacity elements, the bonding contact points being evenly distributed over the surface of the lower functional capacity elements, whereby a high functional capacity element having a high degree of logic gate utilization and shortened average interconnect distances and propagation delays is produced.
Claim 3
Dependent Claim
35 words
The three dimensionally extendible system of claim 1, further comprising: a plurality of input/output bonding pads on the lower capacity elements for electrically connecting the lower capacity elements to external pins on a mounting package.
Claim 4
Dependent Claim
17 words
The three dimensionally extendible system of claim 1, wherein the lower functional capacity units are gate arrays.
Claim 5
Dependent Claim
15 words
The three dimensionally extendible system of claim 3, wherein the gate arrays are field-programmable-gate-arrays (FPGAs).
Claim 6
Dependent Claim
54 words
The three dimensionally extendible system of claim 1, wherein the lower functional capacity elements have a peripheral region and an interior, and further, wherein an added bonding contact point is placed on the peripheral region of the lower functional capacity elements to allow mounting and interconnection of the lower capacity elements to the substrate.
Claim 7
Dependent Claim
54 words
The three dimensionally extendible system of claim 1, wherein the lower functional capacity elements have a peripheral region and an interior, and further, wherein an added bonding contact point is placed in the internal region of the lower functional capacity elements to allow mounting and interconnection of the lower capacity elements to the substrate.
Claim 8
Dependent Claim
41 words
The three dimensionally extendible system of claim 1, further comprising: an insulating layer placed between a lower functional capacity element and an added bonding contact point, wherein the added bonding contact point is electrically connected to the lower functional capacity element.
Claim 9
Dependent Claim
205 words
A multi-chip-module package comprising: a substrate having bonding pads for mounting a plurality of lower functional capacity elements, the bonding pads serving to electrically connect the lower functional capacity elements to the substrate and to an interconnect network on or within the substrate, wherein the interconnection network electrically connects a first contact point on a first lower functional capacity element to a second contact point on the first lower functional capacity element, and further wherein, the interconnection network electrically connects a third contact point on the first lower functional capacity element to a fourth contact point on a second lower functional capacity element; and a plurality of lower functional capacity elements mounted on the substrate to combine said elements into a higher functional capacity element, the lower functional capacity elements including a plurality of logic gates and being adapted to allow mounting and interconnection thereof to the substrate by the inclusion of a plurality of bonding contact points placed on the lower functional capacity elements, the bonding contact points being evenly distributed over the surface of the lower functional capacity elements, whereby a high functional capacity element having a high degree of logic gate utilization and shortened average interconnect distances and propagation delays is produced.
Claim 10
Dependent Claim
205 words
A multi-chip-module package comprising: a substrate having bonding pads for mounting a plurality of lower functional capacity elements, the bonding pads serving to electrically connect the lower functional capacity elements to the substrate and to an interconnect network on or within the substrate, wherein the interconnection network electrically connects a first contact point on a first lower functional capacity element to a second contact point on the first lower functional capacity element, and further wherein, the interconnection network electrically connects a third contact point on the first lower functional capacity element to a fourth contact point on a second lower functional capacity element; and a plurality of lower functional capacity elements mounted on the substrate to combine said elements into a higher functional capacity element, the lower functional capacity elements including a plurality of logic gates and being adapted to allow mounting and interconnection thereof to the substrate by the inclusion of a plurality of bonding contact points placed on the lower functional capacity elements, the bonding contact points being evenly distributed over the surface of the lower functional capacity elements, whereby a high functional capacity element having a high degree of logic gate utilization and shortened average interconnect distances and propagation delays is produced.
Claim 11
Dependent Claim
33 words
The multi-chip-module package of claim 8, further comprising: a plurality of input/output bonding pads on the lower capacity elements for electrically connecting the lower capacity elements to external pins on a mounting package.
Claim 12
Dependent Claim
15 words
The multi-chip-module package of claim 8, wherein the lower functional capacity units are gate arrays.
Claim 13
Dependent Claim
13 words
The multi-chip-module package of claim 10, wherein the gate arrays are field-programmable-gate-arrays (FPGAs).
Claim 14
Dependent Claim
52 words
The multi-chip-module package of claim 8, wherein the lower functional capacity elements have a peripheral region and an interior, and further, wherein an added bonding contact point is placed on the peripheral region of the lower functional capacity elements to allow mounting and interconnection of the lower capacity elements to the substrate.
Claim 15
Dependent Claim
52 words
The multi-chip-module package of claim 8, wherein the lower functional capacity elements have a peripheral region and an interior, and further, wherein an added bonding contact point is placed in the internal region of the lower functional capacity elements to allow mounting and interconnection of the lower capacity elements to the substrate.
Claim 16
Dependent Claim
39 words
The multi-chip-module package of claim 8, further comprising: an insulating layer placed between a lower functional capacity element and an added bonding contact point, wherein the added bonding contact point is electrically connected to the lower functional capacity element.
Claim 17
Dependent Claim
85 words
The three dimensionally extendible system of claim 1, wherein each of the bonding contact points on each of the lower functional capacity elements has a unique identifier associated therewith, with the same identifier being assigned to equivalent contact points on different lower capacity elements, and further wherein, the interconnect network electrically connects a contact point having a given identifier on a first one of the lower capacity elements to a contact point having the same identifier on a second one of the lower capacity elements.
References Cited (Backward Citations)
US4467400A
Cited
US4864381A
Cited
US5257166A
Cited
US5229629A
Cited
EP0475269A2
Cited
EP0592111A2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-06 | 2000-02-05 | 2000-08-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-06 | 2004-02-05 | 2004-08-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-06 | 2008-02-05 | 2008-08-06 | $7700.00 | Window Closed / Lapsed |