Process and structure for measuring the planarity degree of a dielectric layer in an integrated circuit and integrated circuit including means for performing said process

Claim 2

A process of measuring the degree of planarity of a dielectric layer in an integrated circuit, comprising the steps of: depositing, onto a dielectric layer to be measured for planarity, a predetermined measure path of a conductive film; depositing, onto a planar surface, a predetermined reference path of said conductive film; measuring the electric resistance through said reference path; measuring the electric resistance through said measure path; and comparing said measured measure path electric resistance with said measured reference path electrical resistance to determine the deviation of said dielectric layer from planarity.

Claim 3

A process according to claim 1, wherein the comparative measure is effected on a Wheatstone bridge arrangement comprising the measure path and three identical reference paths.

Claim 4

A process according to claim 2, wherein the measure and reference paths are formed on the same integrated circuit, the former onto the portion thereof to be measured for planarity and the latter onto perfectly planar portions.

Claim 5

A process according to claim 3, wherein the perfectly planar portions having the reference paths deposited thereon are peripheral portions of the integrated circuit.

Claim 6

An integrated circuit comprising a continuous substrate, a discontinuous intermediate layer disposed over a portion of the substrate, a dielectric layer deposited onto the substrate and the discontinuous intermediate layer, said dielectric layer having a surface to be tested for planarity, characterized in that it comprises a measure path of a conductive film deposited across said surface of the dielectric layer at the location of the portion with the discontinuous intermediate layer, reference path of said conductive film being identical with said measure path and deposited onto a perfectly planar portion of the integrated circuit, said reference path providing a resistance indication of a planar surface, said measure path providing a resistance indicative of the deviation from planarity of said surface when said measure path resistance is compared to said reference path resistance.

Claim 7

An integrated circuit comprising a continuous substrate, a discontinuous intermediate layer disposed over a portion of the substrate, a dielectric layer deposited onto the substrate and the discontinuous intermediate layer, said dielectric layer having a surface to be tested for planarity, characterized in that it comprises a measure path of a conductive film deposited across said surface of the dielectric layer at the location of the portion with the discontinuous intermediate layer, reference path of said conductive film being identical with said measure path and deposited onto a perfectly planar portion of the integrated circuit, said reference path providing a resistance indication of a planar surface, said measure path providing a resistance indicative of the deviation from planarity of said surface when said measure path resistance is compared to said reference path resistance.

Claim 8

An integrated circuit according to claim 5 and including said measure path and three such reference paths electrically connected to one another into a Wheatstone bridge arrangement.

Claim 9

An integrated circuit according to claim 6, wherein the three reference paths are formed on peripheral portions of the integrated circuit.

Claim 10

An integrated circuit comprising: a substrate; a layer overlaying the surface of said substrate; a dielectric layer overlaying said layer and said substrate; a reference conductive film deposited on said dielectric layer overlaying said substrate; a measurement conductive film deposited upon said dielectric layer overlaying said layer to permit the measurement of planarity of said dielectric layer; and means for determining the planarity of said dielectric layer by measuring the resistance of said measurement conductive film and the resistance of said reference conductive film, a comparison between said measurement conductive film resistance and said reference conductive film resistance being indicative of a deviation from planarity of said dielectric layer overlaying said layer.

Claim 11

An integrated circuit comprising: a substrate; a layer overlaying the surface of said substrate; a dielectric layer overlaying said layer and said substrate; a reference conductive film deposited on said dielectric layer overlaying said substrate; a measurement conductive film deposited upon said dielectric layer overlaying said layer to permit the measurement of planarity of said dielectric layer; and means for determining the planarity of said dielectric layer by measuring the resistance of said measurement conductive film and the resistance of said reference conductive film, a comparison between said measurement conductive film resistance and said reference conductive film resistance being indicative of a deviation from planarity of said dielectric layer overlaying said layer.

Claim 12

The circuit of claim 8 wherein said reference conductive film comprises three conductive film portions, said comparison being performed by a Wheatstone bridge using the resistance of said three reference portions and the resistance of said measurement conductive film deposited on said dielectric layer deposited over said layer.

Claim 13

An integrated circuit comprising: a substrate; a layer overlaying the surface of said substrate; a dielectric layer overlaying said layer and said substrate; a measurement conductive film strip deposited on a measurement portion of said dielectric layer, said measurement portion overlaying said layer; a planar reference conductive film strip deposited on a planar reference portion of said dielectric layer, said reference portion overlaying said substrate; and electrode terminals electrically connected to the measurement conductive film and reference conductive film, respectively, the electrode terminals being adapted to be contacted by a resistance measuring device that measures the resistance of said measurement conductive film strip and said planar reference conductive film strip, respectively, the resistance difference between the measurement conductive film and the planar reference conductive film being a measurement of the deviation from planarity of said dielectric layer overlaying said layer.

Claim 14

An integrated circuit comprising: a substrate; a layer overlaying the surface of said substrate; a dielectric layer overlaying said layer and said substrate; a measurement conductive film strip deposited on a measurement portion of said dielectric layer, said measurement portion overlaying said layer; a planar reference conductive film strip deposited on a planar reference portion of said dielectric layer, said reference portion overlaying said substrate; and electrode terminals electrically connected to the measurement conductive film and reference conductive film, respectively, the electrode terminals being adapted to be contacted by a resistance measuring device that measures the resistance of said measurement conductive film strip and said planar reference conductive film strip, respectively, the resistance difference between the measurement conductive film and the planar reference conductive film being a measurement of the deviation from planarity of said dielectric layer overlaying said layer.

Claim 15

The integrated circuit according to claim 10, wherein the reference conductive film strip is positioned adjacent the measurement conductive film strip and three electrode terminals are provided, one electrode terminal being electrically connected in common to the measurement conductive film strip and the reference conductive film strip and the other two electrodes being connected to different ends of the measurement conductive strip and the reference conductive strip, respectively.

Claim 16

The integrated circuit according to claim 10, wherein said reference conductive film includes first, second, and third reference portions, said first reference portion being electrically coupled to a first end of said measurement conductive film and having one electrode terminal electrically connected thereto, said second reference portion being electrically coupled to a second end of said measurement conductive film and having another electrode terminal electrically connected thereto, and said third reference portion being electrically coupled to said first reference portion and said second reference portion and having an electrode terminal electrically connected between the first and third reference portions and the second and third reference portions, respectively.

Claim 17

The integrated circuit according to claim 10 wherein said electrode terminals, measurement conductive strip, and reference conductive strip are all formed from the same integral conductive strip that extends over different regions of the substrate.

Claim 18

The integrated circuit according to claim 10 wherein the electrode terminals are planar metallic pads that are electrically exposed and are positioned for contact by an external probe that is adapted to apply power to measure the resistance of the measurement conductive strip and the reference conductive strip.

Claim 21

The method of claim 15 wherein said planar reference conductive film comprises a plurality of conductive film portions each having a substantially identical planar reference resistance, said step of comparing being performed by comparing said plurality of planar reference resistances to said measurement resistance.