US5541428A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device with superimposed storage electrodes
Assignee: DOCUPORT (JERSEY) Ltd
•
Filing: 1994-12-08
•
Granted: 1996-07-30
•
Expires: 2014-12-08
Abstract
Abstract In a semiconductor memory device, storage electrodes of two memory cells adjacent to each other are superimposed with each other, with their contours being substantially aligned. As a result, the storage electrodes are extended to cover two memory cell regions. The superimposed storage electrodes are electrically insulated from each other, and the upper storage electrode extends through the lower storage electrode.
Inventors
- 👤 Yoshiki Nagatomo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:36
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/318; H10B12/01; Y; Y10; Y10S; Y10S257/00; Y10S257/908
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
146 words
A semiconductor memory device including plural memory cells provided on an underlying layer, storage electrodes for each said memory cell, and a cell plate opposed to said storage electrodes with a capacitor dielectric film therebetween, wherein: said storage electrodes for plural adjacent said memory cells being superimposed relative to each other, said superimposed storage electrodes having contours defined by respective outer edges, said contours of said superimposed storage electrodes being substantially entirely aligned; and said superimposed storage electrodes being insulated from each other and having respective parts that are electrically connected to said underlying layer, said part of each said superimposed storage electrode, other than said part of a lowermost said storage electrode positioned closest to said underlying layer, extending through and being insulated from at least one other said storage electrode that is positioned closer to said underlying layer than is said each storage electrode.
Claim 2
Dependent Claim
146 words
A semiconductor memory device including plural memory cells provided on an underlying layer, storage electrodes for each said memory cell, and a cell plate opposed to said storage electrodes with a capacitor dielectric film therebetween, wherein: said storage electrodes for plural adjacent said memory cells being superimposed relative to each other, said superimposed storage electrodes having contours defined by respective outer edges, said contours of said superimposed storage electrodes being substantially entirely aligned; and said superimposed storage electrodes being insulated from each other and having respective parts that are electrically connected to said underlying layer, said part of each said superimposed storage electrode, other than said part of a lowermost said storage electrode positioned closest to said underlying layer, extending through and being insulated from at least one other said storage electrode that is positioned closer to said underlying layer than is said each storage electrode.
Claim 3
Dependent Claim
24 words
A semiconductor memory device as claimed in claim 1, wherein said superimposed storage electrodes extend to cover regions of said plural adjacent memory cells.
Claim 4
Dependent Claim
26 words
A semiconductor memory device as claimed in claim 1, wherein said plural adjacent memory cells are aligned in a direction of data lines of said device.
Claim 5
Dependent Claim
26 words
A semiconductor memory device as claimed in claim 1, wherein said plural adjacent memory cells are aligned in a direction of word lines of said device.
Claim 6
Dependent Claim
27 words
A semiconductor memory device as claimed in claim 1, wherein said contours of said superimposed storage electrodes result from and are defined by a common photolithography treatment.
Claim 7
Dependent Claim
33 words
A semiconductor memory device as claimed in claim 1, wherein said part of said each superimposed storage electrode extends through a contact hole formed in said at least one other said storage electrode.
References Cited (Backward Citations)
US5103275A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-30 | 2000-01-29 | 2000-07-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-30 | 2004-01-29 | 2004-07-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-30 | 2008-01-29 | 2008-07-30 | $7700.00 | Window Closed / Lapsed |