US5539688A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fast pre-programming circuit for floating gate memory
Assignee: Macronix International Co Ltd
•
Filing: 1995-05-18
•
Granted: 1996-07-23
•
Expires: 2015-05-18
Abstract
Abstract A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.
Inventors
- 👤 Tom D. Yiu
- 👤 Ray L. Wan
- 👤 Ling-Wen Hsiao
- 👤 Tien-Ler Lin
- 👤 Fuchia Shone
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 00:58
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/12; G11C16/14; G11C16/16; G11C16/24
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
181 words
An integrated circuit memory comprising: a memory array of floating gate memory cells having control gates, floating gates, sources and drains; a plurality of bitlines, the plurality of bitlines arranged in a plurality of byte-wide sets of bitlines, each bitline coupled to the drains of a column of cells in the memory array; a plurality of wordlines, each coupled to the control gates of a row of cells in the memory array; a plurality of source lines, coupled to the sources of a plurality of cells in the memory array; pre-programming circuits, coupled to the plurality of bitlines and the plurality of wordlines, to apply a gate programming potential to a subset having more than one member of the plurality of wordlines, and a data-in programming potential to at least one of the byte-wide sets of bitlines to program a plurality of bytes of selected cells during a pre-programming interval; and erasing circuits, coupled to the plurality of wordlines and the plurality of source lines, to apply an erasing potential to a plurality of pre-programmed memory cells after the pre-programming interval.
Claim 2
Dependent Claim
181 words
An integrated circuit memory comprising: a memory array of floating gate memory cells having control gates, floating gates, sources and drains; a plurality of bitlines, the plurality of bitlines arranged in a plurality of byte-wide sets of bitlines, each bitline coupled to the drains of a column of cells in the memory array; a plurality of wordlines, each coupled to the control gates of a row of cells in the memory array; a plurality of source lines, coupled to the sources of a plurality of cells in the memory array; pre-programming circuits, coupled to the plurality of bitlines and the plurality of wordlines, to apply a gate programming potential to a subset having more than one member of the plurality of wordlines, and a data-in programming potential to at least one of the byte-wide sets of bitlines to program a plurality of bytes of selected cells during a pre-programming interval; and erasing circuits, coupled to the plurality of wordlines and the plurality of source lines, to apply an erasing potential to a plurality of pre-programmed memory cells after the pre-programming interval.
Claim 3
Dependent Claim
36 words
The integrated circuit memory of the claim 1 wherein the pre-programming circuits include a circuit coupled with the plurality of bitlines to reduce load resistance of the at least one byte-wide set of bitlines during pre-programming.
Claim 4
Dependent Claim
18 words
The integrated circuit memory of claim 1, wherein the subset of the plurality of wordlines includes four members.
Claim 5
Dependent Claim
86 words
The integrated circuit memory of claim 1, wherein the pre-programming circuits include: a voltage supply circuit, coupled to the plurality of wordlines, to supply the gate programming potential to control gates of floating gate memory cells coupled to the plurality of wordlines; and control circuits, coupled to the voltage supply circuit to control the voltage supply circuit to vary the gate programming potential during the pre-programming interval as function of time in order to decrease time required to pre-program the plurality of bytes of selected cells.
Claim 6
Dependent Claim
39 words
The integrated circuit memory of claim 4, wherein the gate programming potential remains substantially constant at a first level for a first particular time interval, and remains substantially constant at a second level for a second particular time interval.
Claim 7
Dependent Claim
26 words
The integrated circuit memory of claim 5, wherein change from the first level to the second level occurs relatively abruptly after the first particular time interval.
Claim 8
Dependent Claim
20 words
The integrated circuit memory of claim 5, wherein change from the first level to the second level occurs relatively gradually.
Claim 9
Dependent Claim
70 words
The integrated circuit memory of claim 4, wherein the pre-programming circuits include a controllable voltage source coupled to the plurality of wordlines to apply a voltage to selected wordlines, and control the gate programming potential by maintaining the voltage on source lines in the plurality of source lines at a substantially constant programming voltage and by controlling the controllable voltage source to vary the voltage applied to the selected wordlines.
Claim 10
Dependent Claim
187 words
An integrated circuit memory, comprising: a memory array of floating gate memory cells having control gates, floating gates, sources and drains; a plurality of bitlines, the plurality of bitlines arranged in a plurality of byte-wide sets of bitlines, each bitline coupled to the drains of a column of cells in the memory array; a plurality of wordlines, each coupled to the control gates of a row of cells in the memory array; a plurality of source lines, coupled to the sources of a plurality of cells in the memory array; pre-programming circuits, coupled to the plurality of bitlines and the plurality of wordlines to apply a gate programming potential to a particular wordline of the plurality of wordlines, and a data-in programming potential to a group having more than one member of the plurality of byte-wide sets of bitlines to program a plurality of selected bytes of cells coupled to the particular wordline during a pre-programming interval; and erasing circuits, coupled to the plurality of wordlines, and the plurality of source lines, to apply an erasing potential to a plurality of pre-programmed cells after the pre-programming interval.
Claim 11
Dependent Claim
187 words
An integrated circuit memory, comprising: a memory array of floating gate memory cells having control gates, floating gates, sources and drains; a plurality of bitlines, the plurality of bitlines arranged in a plurality of byte-wide sets of bitlines, each bitline coupled to the drains of a column of cells in the memory array; a plurality of wordlines, each coupled to the control gates of a row of cells in the memory array; a plurality of source lines, coupled to the sources of a plurality of cells in the memory array; pre-programming circuits, coupled to the plurality of bitlines and the plurality of wordlines to apply a gate programming potential to a particular wordline of the plurality of wordlines, and a data-in programming potential to a group having more than one member of the plurality of byte-wide sets of bitlines to program a plurality of selected bytes of cells coupled to the particular wordline during a pre-programming interval; and erasing circuits, coupled to the plurality of wordlines, and the plurality of source lines, to apply an erasing potential to a plurality of pre-programmed cells after the pre-programming interval.
Claim 12
Dependent Claim
18 words
The integrated circuit memory of claim 9, wherein the group of byte-wide sets of bitlines includes four members.
Claim 13
Dependent Claim
35 words
The integrated circuit memory of claim 9, wherein the pre-programming circuits include a circuit coupled with the plurality of bitlines to reduce load resistance of the group of byte wide sets of bitlines during pre-programming.
Claim 14
Dependent Claim
84 words
The integrated circuit memory of claim 9, wherein the pre-programming circuits include: a voltage supply circuit, coupled to the plurality of wordlines, to supply the gate programming potential to control gates of memory cells coupled to the plurality of wordlines; and control circuits, coupled to the voltage supply circuit to control the voltage supply circuit to vary the gate programming potential during the pre-programming interval as function of time in order to decrease time required to pre-program the plurality of selected bytes of cells.
Claim 15
Dependent Claim
39 words
The integrated circuit memory of claim 12, wherein the gate programming potential remains substantially constant at a first level for a first particular time interval, and remains substantially constant at a second level for a second particular time interval.
Claim 16
Dependent Claim
26 words
The integrated circuit memory of claim 13, wherein change from the first level to the second level occurs relatively abruptly after the first particular time interval.
Claim 17
Dependent Claim
20 words
The integrated circuit memory of claim 13, wherein change from the first level to the second level occurs relatively gradually.
Claim 18
Dependent Claim
70 words
The integrated circuit memory of claim 12, wherein the pre-programming circuits include a controllable voltage source coupled to the plurality of wordlines to apply a voltage to selected wordlines, and control the gate programming potential by maintaining the voltage on source lines in the plurality of source lines at a substantially constant programming voltage and by controlling the controllable voltage source to vary the voltage applied to the selected wordlines.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-23 | 2000-01-22 | 2000-07-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-23 | 2004-01-22 | 2004-07-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-23 | 2008-01-22 | 2008-07-23 | $7700.00 | Window Closed / Lapsed |