US5537609A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Mini cache operational module for enhancement to general cache
Assignee: Unisys Corp
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Filing: 1995-10-24
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Granted: 1996-07-16
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Expires: 2015-10-24
Abstract
Abstract A mini-cache module is added to a computer system to increase throughput or may also be added to enhance the functionality of a general cache memory unit. The mini-cache module refills and stores frequently used data words concurrently during processor operations and provides them to the processor, eliminating the need to access a system bus to main memory. A data queue storage stores a data block of words from main memory and makes them available to requests from the main processor (if the requested address matches an address register block in the mini-cache). If an address "hit" occurs, then the mini-cache will prevent any system bus request to main memory and additionally will monitor the system bus for any "Write" operations which might feasibly change the validity of data in the data storage block of the mini-cache. In this case the data stored in the mini-cache is invalidated and cannot be used by the processor.
Inventors
- 👤 Bruce E. Whittaker
- 👤 Leland E. Watson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 16:02
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0893; G06F12/0897
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
325 words
A system wherein a processor having a general cache memory is connected to an auxiliary cache module for enhancing cache storage of said general cache memory to expand the storage capability of frequently used words from main memory and which words have a main memory address, said processor generating commands for reading data words or instruction code words, said system comprising: (a) said auxiliary cache module including: (a1) steering block means for routing the addresses of a block of four words, to an internal address register means and for transferring said block of four words to a data queue means for storage during such time when said processor is executing processing instructions; (a2) said data queue means for storing said block of four words from main memory, said words including data words and instruction code words: (a3) said internal address register means for holding the said main memory address of each of said block of four words; (a4) means to compare a single word requested address from said processor with the addresses stored in said internal address register means and to generate a hit signal if a match occurs, for enabling a word transfer to said processor; (b) bus interface means connecting to said main memory via a system bus means including: (b1) means for transferring a four-word block of data words or instruction code words to said steering block means; (c) internal maintenance means for receiving control signals to configure the storage capability of said general cache memory and said auxiliary cache module so as to enable said auxiliary cache module to expand the storage capacity of said general cache memory, or to disable said auxiliary cache module from expanding the storage capacity of said general cache memory, and including: (c1) means to enable said data queue means to respond only to Read data word commands only; (c2) means to enable said data queue means to respond only to Read instruction code word commands.
Claim 2
Independent Claim
325 words
A system wherein a processor having a general cache memory is connected to an auxiliary cache module for enhancing cache storage of said general cache memory to expand the storage capability of frequently used words from main memory and which words have a main memory address, said processor generating commands for reading data words or instruction code words, said system comprising: (a) said auxiliary cache module including: (a1) steering block means for routing the addresses of a block of four words, to an internal address register means and for transferring said block of four words to a data queue means for storage during such time when said processor is executing processing instructions; (a2) said data queue means for storing said block of four words from main memory, said words including data words and instruction code words: (a3) said internal address register means for holding the said main memory address of each of said block of four words; (a4) means to compare a single word requested address from said processor with the addresses stored in said internal address register means and to generate a hit signal if a match occurs, for enabling a word transfer to said processor; (b) bus interface means connecting to said main memory via a system bus means including: (b1) means for transferring a four-word block of data words or instruction code words to said steering block means; (c) internal maintenance means for receiving control signals to configure the storage capability of said general cache memory and said auxiliary cache module so as to enable said auxiliary cache module to expand the storage capacity of said general cache memory, or to disable said auxiliary cache module from expanding the storage capacity of said general cache memory, and including: (c1) means to enable said data queue means to respond only to Read data word commands only; (c2) means to enable said data queue means to respond only to Read instruction code word commands.
Claim 3
Dependent Claim
31 words
The system of claim 1 wherein said steering block means includes: (a) means to address and select a single requested word from said block of words in said data queue means.
Claim 4
Dependent Claim
34 words
The system of claim 1 wherein said data queue means includes: (a) signal bit register means for each word in said block of words to indicate whether its associated word is invalid or valid.
Claim 5
Dependent Claim
102 words
The system of claim 1 wherein said auxiliary cache module includes: (a) means to sense when an external write operation to a requested selected address in main memory, is in progress, which matches the address in said internal address register means, including: (a1) means to signal an invalidation circuit means when said match occurs; (b) said invalidation circuit means for setting an invalid signal in said internal address register means, upon occurrence of said matched address signal; (c) and wherein said internal address register means includes a flip-flop for indicating the validity/invalidity of said matched address in said internal address register means.
Claim 6
Dependent Claim
29 words
The system of claim 4 wherein said means to compare includes: (a) means to inhibit a request to main memory by said processor upon occurrence of said match signal.
Claim 7
Dependent Claim
31 words
The system of claim 1 wherein said steering block means includes: (a) means for selecting which one word of said block of four words will be transmitted to a requesting processor.
Claim 8
Dependent Claim
236 words
In a very large scale integrated circuit chip having predetermined internal logic units and gates which can be controlled externally to reconfigure the said internal logic units and gates, a reconfigurable system having a processor, a general cache and a bus interface unit with an auxiliary mini cache means, said system comprising: (a) processor means for executing instruction code or data words derived from a main memory means or from instruction code words and data words residing in a general cache means or auxiliary mini cache means; (b) general cache means for storing frequently used instruction code words and data words for immediate and quick access by said processor means; (c) said bus interface unit for connecting said main memory means to said auxiliary mini cache means and wherein said auxiliary mini cache means is connected to said general cache means for providing supplementary storage for said frequently used instruction code words and data words, said mini cache means including: (c1) maintenance circuit means for receiving control signals from an external source, said maintenance circuit means including (i) means to expand cache storage by enablement of said auxiliary cache means to provide extra storage for said general cache means, and (ii) means to disable said auxiliary mini cache means to deny extra storage for said general cache means; (c2) means for receiving a four-word block of data or code words during periods of normal processor operations.
Claim 9
Dependent Claim
236 words
In a very large scale integrated circuit chip having predetermined internal logic units and gates which can be controlled externally to reconfigure the said internal logic units and gates, a reconfigurable system having a processor, a general cache and a bus interface unit with an auxiliary mini cache means, said system comprising: (a) processor means for executing instruction code or data words derived from a main memory means or from instruction code words and data words residing in a general cache means or auxiliary mini cache means; (b) general cache means for storing frequently used instruction code words and data words for immediate and quick access by said processor means; (c) said bus interface unit for connecting said main memory means to said auxiliary mini cache means and wherein said auxiliary mini cache means is connected to said general cache means for providing supplementary storage for said frequently used instruction code words and data words, said mini cache means including: (c1) maintenance circuit means for receiving control signals from an external source, said maintenance circuit means including (i) means to expand cache storage by enablement of said auxiliary cache means to provide extra storage for said general cache means, and (ii) means to disable said auxiliary mini cache means to deny extra storage for said general cache means; (c2) means for receiving a four-word block of data or code words during periods of normal processor operations.
Claim 10
Dependent Claim
38 words
The system of claim 7 wherein said maintenance circuit means includes: (a) means to load input test data into said predetermined logic units and gates; (b) means to shift out said input test data for test and diagnosis.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-16 | 2000-01-15 | 2000-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-16 | 2004-01-15 | 2004-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-16 | 2008-01-15 | 2008-07-16 | $7700.00 | Window Closed / Lapsed |