US5535220A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Forward error correcting transmitter and receiver
Assignee: Panasonic Holdings Corp
•
Filing: 1994-01-19
•
Granted: 1996-07-09
•
Expires: 2014-01-19
Abstract
Abstract A forward error correcting transmitter and receiver for preventing the erroneous detection of synchronization is provided in a system in which synchronization of an interleaver circuit and a deinterleaver circuit, to be inserted between a convolutional encoder and a Viterbi decoder, is obtained from a synchronization detecting circuit of the Viterbi decoder. A LFSR (Linear Feedback Shift Register) is used as a row-direction address counter during writing and an up/down counter is used as a column-direction address counter during reading, during the interleaver circuit. In the deinterleaver circuit, an up/down counter is used as the column-direction address counter during writing, and an LFSR is used as the row-direction address counter during reading.
Inventors
- 👤 Ippei Kanno
- 👤 Seiji Sakashita
- 👤 Hiroaki Ozeki
- 👤 Daisuke Hayashi
- 👤 Todd S. Bowser
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:32
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/004; H04L1/0056; H04L1/0071; H03; H03M; H03M13/00; H03M13/27; H03M13/2703; H03M13/271; H03M13/276; H03M13/33; H04L1/0041; H04L1/0042; H04L1/0045; H04L1/0054; H04L7/00; H04L7/04; H04L7/048
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
149 words
A forward error correcting transmitter which comprises: an error correcting encoder, said error correcting encoder error-correcting-encoding a digital signal to obtain an error-correcting-encoded signal; an interleaver comprising: a memory, composed of rows and columns, for permitting the reading and writing of said error-correcting-encoded signal; and a memory controller, said memory controller controlling said memory, when writing in said memory, so as to write said error-correcting-encoded signal on a row by row basis in a predetermined random sequence in each row, and controls said memory, when reading out from said memory, so as to read out said error-correcting-encoded signal written in said memory in one direction in each column, alternately reversing the direction on a column by column basis; a modulator, said modulator modulating said error-correcting-encoded signal read out from said memory to obtain a modulated signal; and a transmitter, said transmitter providing a transmitted signal from said modulated signal.
Claim 2
Dependent Claim
149 words
A forward error correcting transmitter which comprises: an error correcting encoder, said error correcting encoder error-correcting-encoding a digital signal to obtain an error-correcting-encoded signal; an interleaver comprising: a memory, composed of rows and columns, for permitting the reading and writing of said error-correcting-encoded signal; and a memory controller, said memory controller controlling said memory, when writing in said memory, so as to write said error-correcting-encoded signal on a row by row basis in a predetermined random sequence in each row, and controls said memory, when reading out from said memory, so as to read out said error-correcting-encoded signal written in said memory in one direction in each column, alternately reversing the direction on a column by column basis; a modulator, said modulator modulating said error-correcting-encoded signal read out from said memory to obtain a modulated signal; and a transmitter, said transmitter providing a transmitted signal from said modulated signal.
Claim 3
Dependent Claim
19 words
A forward error correcting transmitter as claimed in claim 1, wherein said predetermined random sequence is an M-series sequence.
Claim 4
Dependent Claim
20 words
A forward error correcting transmitter as claimed in claim 1, wherein said predetermined random sequence is continuous in one direction.
Claim 5
Dependent Claim
151 words
A forward error correcting receiver which comprises: a receiver, said receiver receiving a transmitted signal; a demodulator, said demodulator demodulating said transmitted signal to obtain an input signal; an deinterleaver comprising: a memory, composed of rows and columns, for permitting the reading and writing of said input signal; and a memory controller, said memory controller controlling said memory, when writing into said memory, so as to write said input signal in one direction in each column, alternately reversing the direction on a column by column basis, and controls said memory, when reading out from said memory, so as to read out said input signal on a row by row basis in a predetermined random sequence in each row; an error correcting decoder, said error correcting decoder error-correcting-decoding said input read out from said memory; and a synchronization detector, said synchronization detector detecting the synchronization of said input signal to be error-correcting-decoded.
Claim 6
Dependent Claim
151 words
A forward error correcting receiver which comprises: a receiver, said receiver receiving a transmitted signal; a demodulator, said demodulator demodulating said transmitted signal to obtain an input signal; an deinterleaver comprising: a memory, composed of rows and columns, for permitting the reading and writing of said input signal; and a memory controller, said memory controller controlling said memory, when writing into said memory, so as to write said input signal in one direction in each column, alternately reversing the direction on a column by column basis, and controls said memory, when reading out from said memory, so as to read out said input signal on a row by row basis in a predetermined random sequence in each row; an error correcting decoder, said error correcting decoder error-correcting-decoding said input read out from said memory; and a synchronization detector, said synchronization detector detecting the synchronization of said input signal to be error-correcting-decoded.
Claim 7
Dependent Claim
22 words
A forward error correcting receiver as claimed in claim 4, wherein said predetermined random sequence represents a maximum length shift register sequence.
Claim 8
Dependent Claim
21 words
A forward error correcting receiver as claimed in claim 4, wherein said predetermined random sequence is continuous in a single direction.
References Cited (Backward Citations)
JPS57113656A
Cited
JPS58181348A
Cited
FR2592258A1
Cited
JPS63181539A
Cited
US5239623A
Cited
US5042033A
Cited
US5313464A
Cited
WO1991012611A1
Cited
US5285458A
Cited
US5309450A
Cited
US5384782A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-09 | 2000-01-08 | 2000-07-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-09 | 2004-01-08 | 2004-07-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-09 | 2008-01-08 | 2008-07-09 | $7700.00 | Window Closed / Lapsed |