Flat cache-only multi-processor architectures

Claim 2

A shared-memory computer system having a plurality of coupled processing nodes, each processing node having a processor for executing software instructions, and a main memory portion of a global shared memory space organized in pages, each page having a plurality of respectively addressed data items, the computer system comprising: a plurality of home processing nodes assigned from the plurality of processing nodes, each data item in the global shared memory space assigned to a home processing node based on the address of the respective data item; for a data item in the global shared memory space, a master processing node from the plurality of processing nodes wherein a current copy of the data item is stored, there being at least one data item in the global shared memory space having its home processing node different from its master processing node; and for each home processing node, a home directory memory located at the home processing node for centralizing directory information for each data item assigned to the home processing node.

Claim 3

The computer system of claim 1 wherein the directory information comprises: an indication of the current state of the data item: a pointer to the master processing node for the data item, the master processing node being the exactly one processing node having a master copy of the data item; and a list of sharer nodes, each sharer node having a copy of the data item.

Claim 4

The computer system of claim 1 wherein the assignments of home processing nodes are essentially uniformly distributed among the processing nodes.

Claim 5

The computer system of claim 1 wherein the home processing nodes are assigned by a hashing function.

Claim 6

The computer system of claim 4 wherein the hashing function is based on the high-order bits of the address in the memory space of each data item.

Claim 7

The computer system of claim 1 wherein the main memory portion of the global shared memory space is an attraction memory cache.

Claim 8

The computer system of claim 6 wherein the main attraction memory cache is divided into a plurality of banks.

Claim 9

The computer system of claim 1 wherein the home directory memory controls dissemination of requests for operations on data items centralized in the home directory.

Claim 10

The computer system of claim 1 further comprising a general interconnection network for coupling the processing nodes.

Claim 13

The method of claim 10 wherein the step of centralizing comprises: maintaining a state for each data item centralized in the home processing node; maintaining a pointer to the master processing node for each data item, the master processing node being the exactly one processing node having a master copy of the data item; and maintaining a sharer list of the processing nodes having a copy of the data item.

Claim 14

The method of claim 10 wherein the step of assigning comprises essentially uniformly distributing the assignments of home processing nodes among the processing nodes based on the address of each data item in the memory space.

Claim 15

The method of claim 12 wherein the step of assigning comprises hashing on the address of the data item.

Claim 16

The method of claim 13 wherein the step of hashing is based on the high-order bits of the address of the data item.

Claim 17

The method of claim 10 further comprising the step of disseminating a request from a requestor processing node to a master processing node, the master processing node being the exactly one processing node having a master copy of the data item.

Claim 18

A shared-memory computer having a plurality of coupled processing nodes, comprising: a) a global shared memory space organized in pages, each page having a plurality of respectively addressed data items; b) a plurality of master processing nodes from the plurality of coupled processing nodes, each master processing node having stored therein a master copy of a data item in the global shared memory space; c) a plurality of home processing nodes from the plurality of coupled processing nodes, each home processing node including: a data processor for executing software instructions; a main memory cache to the global shared memory space; a plurality of assigned data items, each assigned data item assigned to the assigned home processing node based on the address of the respective data item; and a directory memory for centralizing directory information for each data item assigned to the assigned home processing node, the directory information including an indication of the master processing node for the respective data item; d) at least one data item having its home processing node differing from its master processing node; and e) a general interconnection network for coupling the processing nodes.

Claim 19

A shared-memory computer having a plurality of coupled processing nodes, comprising: a) a global shared memory space organized in pages, each page having a plurality of respectively addressed data items; b) a plurality of master processing nodes from the plurality of coupled processing nodes, each master processing node having stored therein a master copy of a data item in the global shared memory space; c) a plurality of home processing nodes from the plurality of coupled processing nodes, each home processing node including: a data processor for executing software instructions; a main memory cache to the global shared memory space; a plurality of assigned data items, each assigned data item assigned to the assigned home processing node based on the address of the respective data item; and a directory memory for centralizing directory information for each data item assigned to the assigned home processing node, the directory information including an indication of the master processing node for the respective data item; d) at least one data item having its home processing node differing from its master processing node; and e) a general interconnection network for coupling the processing nodes.

Claim 20

The computer of claim 16 wherein the directory memory comprises: a state memory for maintaining the current state of each data item assigned to the processing node; a pointer to the master processing node for each data item, the master processing node being the exactly one processing node having a master copy of the data item; and a list of sharer nodes, each sharer node having a copy of the data item.

Claim 21

The computer of claim 16 wherein the main memory cache is organized as an attraction memory.

Claim 22

The computer of claim 18 wherein the attraction memory is not backed-up by physical memory.

Claim 23

The computer of claim 16 wherein there is one home processing node assigned for each addressed data item.

Claim 26

The method of claim 21 wherein the first access request is a read access request and further comprising the step of adding the local processing node to a list of processing nodes having read access to the data item, the list maintained in the home processing node.

Claim 27

The method of claim 21 wherein the first access request is a write access request and further comprising the steps of: invalidating shared copies of the data item, the shared copies of the data item being on at least one processing node other than the local processing node; and designating the local processing node as the master processing node.

Claim 28

The method of claim 23 wherein the step of invalidating comprises invalidated the copy of the data item on the master processing node.

Claim 29

The method of claim 21 further comprising a step of transmitting an acknowledgement message from the local processing node to the home processing node to acknowledge receipt of the copy of the data item.

Claim 30

The method of claim 21 wherein the second access request is a duplicate of the first access request.

Claim 31

A shared-memory computer system having a plurality of coupled processing nodes, each processing node having a processor for executing software instructions, a main memory portion of a global shared memory space organized in pages, each page having a plurality of respectively addressed data items, the computer system comprising: a plurality of home processing nodes assigned from the plurality of processing nodes, each data item assigned to a home processing node by a hashing function based on the address of each data item; and for each home processing node, a home directory memory located at the home processing node for centralizing directory information for each data item assigned to the home processing node, each data item residing in a master processing node from the plurality of processing nodes.

Claim 32

A shared-memory computer system having a plurality of coupled processing nodes, each processing node having a processor for executing software instructions, a main memory portion of a global shared memory space organized in pages, each page having a plurality of respectively addressed data items, the computer system comprising: a plurality of home processing nodes assigned from the plurality of processing nodes, each data item assigned to a home processing node by a hashing function based on the address of each data item; and for each home processing node, a home directory memory located at the home processing node for centralizing directory information for each data item assigned to the home processing node, each data item residing in a master processing node from the plurality of processing nodes.

Claim 33

The computer system of claim 27 wherein the directory information comprises: an indication of the current state of the data item: a pointer to the master processing node for the data item, the master processing node being the exactly one processing node having a master copy of the data item; and a list of sharer nodes, each sharer node having a copy of the data item.

Claim 34

The computer system of claim 27 wherein the assignments of home processing nodes are essentially uniformly distributed among the processing nodes.

Claim 35

The computer system of claim 27 wherein there is at least one data item in the global shared memory space which has its home processing node different from its master processing node.

Claim 36

The computer system of claim 27 wherein the main memory portion of the global shared memory space is an attraction memory cache.

Claim 37

The computer system of claim 27 wherein the home directory memory controls dissemination of requests for operations on data items centralized in the home directory.

Claim 38

The computer system of claim 27 further comprising a general interconnection network for coupling the processing nodes.

Claim 41

The method of claim 34 wherein the step of centralizing comprises: maintaining a state for each data item centralized in the home processing node; maintaining a pointer to the master processing node for each data item, the master processing node being the exactly one processing node having a master copy of the data item; and maintaining a sharer list of the processing nodes having a copy of the data item.

Claim 42

The method of claim 34 wherein the step of assigning comprises essentially uniformly distributing the assignments of home processing nodes among the processing nodes.

Claim 43

The method of claim 34 further comprising the step of providing at least one data item having its home processing node different from its master processing node.

Claim 44

The method of claim 34 further comprising the step of disseminating a request from a requestor processing node to a master processing node, the master processing node being the exactly one processing node having a master copy of the data item.