Single twist layout and method for paired line conductors of integrated circuits

Claim 2

An interconnection array comprising: a plurality of paired line conductors, each pair comprising a true line conductor and an associated complement line conductor; said plurality of paired line conductors being substantially parallel within a first region and within a second region; said plurality of paired line conductors crossing in a crossing region disposed between said first region and said second region; said plurality of paired line conductors being located in said first region and said second region and being crossed in said crossing region such that no true line conductor is immediately adjacent to its associated complement line conductor in said first region and said second region; and, said plurality of paired line conductors further being located in said first region and said second region and being crossed in said crossing region such that for any given line conductor of said plurality of line conductors, capacitive coupling occurring in said first region and said second region between said given line conductor and immediately adjacent true line conductors of said plurality of line conductors is balanced by capacitive coupling occurring in said first region and said second region between said given line conductor and immediately adjacent complement line conductors associated with said immediately adjacent true line conductors.

Claim 3

The interconnection array of claim 1, wherein a first paired line conductor is disposed adjacent to an edge of the interconnection array in said first region, and wherein the complement line conductor of said first paired line conductor is disposed adjacent to a "dummy line conductor", said "dummy line conductor" being separate from said plurality of paired line conductors.

Claim 4

The interconnection array of claim 1, wherein first paired line conductors and second paired line conductors form a pattern in said crossing region and wherein said pattern is repeated in said interconnection array for additional pairs of paired line conductors of said plurality of paired line conductors.

Claim 5

The interconnection array of claim 1, wherein said crossing region is substantially transverse said plurality of line conductors of said first region and of said second region.

Claim 6

The interconnection array of claim 1, wherein said interconnection array comprises a substantially planar array and the center-to-center spacing between adjacent line conductors of said plurality of paired line conductors comprises one "pitch", and wherein multiple line conductors of said plurality of paired line conductors are offset "up" or "down" in said second region relative to said first region.

Claim 7

The interconnection array of claim 5, wherein said pattern comprises: a first line conductor offset one pitch "down" in said second region relative to said first region; a second line conductor located one pitch "down" from said first line conductor in said first region and offset three pitches "down" in said second region; a third line conductor which is the complement of said first line conductor, located two pitches "down" from said first line conductor in said first region and offset three pitches "up" in said second region; and a fourth line conductor which is the complement of said second line conductor, located three pitches "down" from said first line conductor in said first region and offset one pitch "up" in said second region.

Claim 8

The interconnection array of claim 5, wherein said pattern comprises: a first line conductor offset zero pitches in said second region relative to said first region; a second line conductor located one pitch "down" from said first line conductor in said first region and offset two pitches "down" in said second region; a third line conductor which is the complement of said first line conductor, located two pitches "down" from said first line conductor in said first region and offset four pitches "up" in said second region; and a fourth line conductor which is the complement of said second line conductor, located three pitches "down" from said first line conductor in said first region and offset two pitches "up" in said second region.

Claim 9

The interconnection array of claim 5, wherein said pattern comprises: a first line conductor offset one pitch "up" in said second region relative to said first region; a second line conductor located one pitch "down" from said first line conductor in said first region and offset one pitch "down" in said second region; a third line conductor which is the complement of said first line conductor, located two pitches "down" from said first line conductor in said first region and offset five pitches "up" in said second region; and a fourth line conductor which is the complement of said second line conductor, located three pitches "down" from said first line conductor in said first region and offset three pitches "up" in said second region.

Claim 10

The interconnection array of claim 5, wherein said pattern comprises: a first line conductor offset two pitches "down" in said second region relative to said first region; a second line conductor located one pitch "down" from said first line conductor in said first region and offset two pitches "down" in said second region; a third line conductor which is the complement of said first line conductor, located two pitches "down" from said first line conductor in said first region and offset two pitches "up" in said second region; and a fourth line conductor which is the complement of said second line conductor, located three pitches "down" from said first line conductor in said first region and offset zero pitches in said second region.

Claim 11

The interconnection array of claim 5, wherein said pattern comprises: a first line conductor offset three pitches "down" in said second region relative to said first region; a second line conductor located one pitch "down" from said first line conductor in said first region and offset six pitches "down" in said second region; a third line conductor which is the complement of said first line conductor, located two pitches "down" from said first line conductor in said first region and offset one pitch "up" in said second region; and a fourth line conductor which is the complement of said second line conductor, located three pitches "down" from said first line conductor in said first region and offset one pitch "down" in said second region.

Claim 12

The interconnection array of claim 1, wherein said interconnection array comprises an array of bit lines within a semiconductor memory array.

Claim 13

The interconnection array of claim 1, wherein said interconnection array comprises an array of bit lines within a dynamic random access memory.

Claim 14

A line conductor layout method for an integrated circuit interconnection array having a plurality of paired line conductors of a given length, said line conductor layout method comprising the steps of: (a) forming a first region of substantially parallel line conductors comprising a plurality of paired line conductors, each pair comprising a true line conductor and an associated complement line conductor; (b) forming a second region of substantially parallel line conductors comprising a plurality of line conductors which correspond to said line conductors of said first region; and (c) forming a crossing region between said first region and said second region, said crossing region comprising a plurality of line conductors providing connections between line conductors of said first region and line conductors of said second region so as to provide a plurality of continuous true and complement line conductors extending from said first region through said crossing region to said second region, said line conductors of said crossing region connecting line conductors of said first region and said second region such that no true line conductor is immediately adjacent to its complement line conductor in said first region and no true line conductor is immediately adjacent to its complement line conductor in said second region, and further such that for any given line conductor of said plurality of line conductors, capacitive coupling occurring in said first region and said second region between said given line conductor and immediately adjacent true line conductors of said plurality of line conductors is balanced by capacitive coupling occurring in said first region and said second region between said given line conductor and immediately adjacent complement line conductors associated with said immediately adjacent true line conductors.

Claim 15

A line conductor layout method for an integrated circuit interconnection array having a plurality of paired line conductors of a given length, said line conductor layout method comprising the steps of: (a) forming a first region of substantially parallel line conductors comprising a plurality of paired line conductors, each pair comprising a true line conductor and an associated complement line conductor; (b) forming a second region of substantially parallel line conductors comprising a plurality of line conductors which correspond to said line conductors of said first region; and (c) forming a crossing region between said first region and said second region, said crossing region comprising a plurality of line conductors providing connections between line conductors of said first region and line conductors of said second region so as to provide a plurality of continuous true and complement line conductors extending from said first region through said crossing region to said second region, said line conductors of said crossing region connecting line conductors of said first region and said second region such that no true line conductor is immediately adjacent to its complement line conductor in said first region and no true line conductor is immediately adjacent to its complement line conductor in said second region, and further such that for any given line conductor of said plurality of line conductors, capacitive coupling occurring in said first region and said second region between said given line conductor and immediately adjacent true line conductors of said plurality of line conductors is balanced by capacitive coupling occurring in said first region and said second region between said given line conductor and immediately adjacent complement line conductors associated with said immediately adjacent true line conductors.

Claim 16

The line conductor layout method of claim 13, wherein said forming step (c) includes establishing a crossing pattern and forming said single crossing region by repeating said crossing pattern for successive pairs of line conductors.

Claim 17

The line conductor layout method of claim 13, wherein said forming steps (a) and (b) comprise forming a first metallization layer, and said forming step (c) comprises forming a second metallization layer to electrically interconnect corresponding line conductors in said first region and said second region.