US5533203A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Start of packet receive interrupt for ethernet controller
Assignee: GlobalFoundries Inc
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Filing: 1995-05-09
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Granted: 1996-07-02
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Expires: 2015-05-09
Abstract
Abstract A system is provided for ensuring that a ethernet controller operates to optimize bus latency and central processing unit (CPU) utilization in a network environment when reviewing data packets. Through the efficient use of a plurality of buffer memories and a driver, the bus utilization in conjunction with the controller the system provides for the receipt and transfer of data packets from the ethernet controller during the latency period of the network. In so doing, the overall performance of the network is enhanced.
Inventors
- 👤 Matthew J. Fischer
- 👤 Glen Gibson
- 👤 Jeffrey Dwork
- 👤 Thomas J. Runaldue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 03:14
CPC Classifications
H; H04; H04L; H04L49/00; H04L49/90; H04L49/9047; H04L49/9052; G; G06; G06F; G06F13/00; G06F13/38; G06F13/10; G06F13/12; G06F13/124; G06F13/128; H04L49/901; H04L49/9021; H04L49/9057; H04L49/9063; H04L49/9068; H04L49/9073; H04L49/9078
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
319 words
A system for increasing the speed at which data is received from a network comprising: a plurality of buffer memory means; an application memory means having a plurality of memory portions; a controller for sequentially writing data received from the network to the plurality of buffer memory means and for generating an interrupt signal when a first buffer memory means is full; a driver means for sequentially transferring data from the plurality of buffer memory means to the plurality of memory portions of the application memory means, the driver means being actuated upon receiving the interrupt signal whereby data transfer from the first buffer memory means to a first portion of the plurality of memory portions of the application memory means is performed while data is being written into a second buffer memory means; a plurality of receive descriptors, the plurality of receive descriptors being set up by the driver means to indicate descriptor ownership status and start of packet status, each receive descriptor being associated with one of the plurality of buffer memory means, descriptor ownership status indicating whether the controller can write to the buffer memory means associated with the receive descriptor, and the start of packet status indicating whether a data packet can begin in the buffer memory means associated with the receive descriptor; wherein the controller polls the plurality of receive descriptors for receive descriptor that indicates ownership of the receive descriptor by the controller and start of packet status before the controller write data into one of the plurality of buffer memory means; wherein the controller updates the receive descriptor to relinguish ownership of the receive descriptor and to change the start of packet status after a particular one of the plurality of buffer memory means is filled; and wherein the controller performs a lookahead polling of a succeeding receive descriptor when a specified byte of the data packet is provided to the controller.
Claim 2
Independent Claim
319 words
A system for increasing the speed at which data is received from a network comprising: a plurality of buffer memory means; an application memory means having a plurality of memory portions; a controller for sequentially writing data received from the network to the plurality of buffer memory means and for generating an interrupt signal when a first buffer memory means is full; a driver means for sequentially transferring data from the plurality of buffer memory means to the plurality of memory portions of the application memory means, the driver means being actuated upon receiving the interrupt signal whereby data transfer from the first buffer memory means to a first portion of the plurality of memory portions of the application memory means is performed while data is being written into a second buffer memory means; a plurality of receive descriptors, the plurality of receive descriptors being set up by the driver means to indicate descriptor ownership status and start of packet status, each receive descriptor being associated with one of the plurality of buffer memory means, descriptor ownership status indicating whether the controller can write to the buffer memory means associated with the receive descriptor, and the start of packet status indicating whether a data packet can begin in the buffer memory means associated with the receive descriptor; wherein the controller polls the plurality of receive descriptors for receive descriptor that indicates ownership of the receive descriptor by the controller and start of packet status before the controller write data into one of the plurality of buffer memory means; wherein the controller updates the receive descriptor to relinguish ownership of the receive descriptor and to change the start of packet status after a particular one of the plurality of buffer memory means is filled; and wherein the controller performs a lookahead polling of a succeeding receive descriptor when a specified byte of the data packet is provided to the controller.
Claim 3
Dependent Claim
16 words
The system of claim 1 wherein the plurality of receive descriptors are in groups of three.
Claim 4
Independent Claim
350 words
A system for increasing the speed at which data is received from a network comprising: a first, second and third buffer memory means; a controller for sequentially writing data received from the network to the first , second and third buffer memory means and for generating an interrupt signal when the first buffer memory means is full; a driver means for transferring data from the first, second and third memory means to a first, second and third portions of an application memory means, respectively, the driver means being actuated upon receiving the interrupt signal whereby data transfer from the first memory means to the first portion of the application memory means is performed while data is being written into the second buffer memory means; a plurality of receive descriptors, the plurality of receive descriptors being set up by the driver means to indicate descriptor ownership status and start of packet status, each receive descriptor being associated with one of the buffer memory means, the descriptor ownership status indicating whether the controller can write to the one of the buffer memory means associated with the receive descriptor, and the start of packet status indicating whether a data packet can begin in the one of the buffer memory means associated with the receive descriptor; wherein the controller polls the plurality of receive descriptors for receive descriptor that indicates ownership of the receive descriptor by the controller and start of packet status before the controller write data into the first, second or third buffer memory means; wherein the controller updates the receive descriptor to relinguish ownership of the receive descriptor and to change the start of packet status after the first, second or third buffer memory means is filled; wherein before beginning the transfer of data from the first, second or third buffer memory means to the first, second or third portion of the application memory means, respectively, the driver means polls for the updated receive descriptors; and wherein the controller performs a lookahead polling of a succeeding receive descriptor when a specified byte of the data packet is provided to the controller.
Claim 5
Independent Claim
350 words
A system for increasing the speed at which data is received from a network comprising: a first, second and third buffer memory means; a controller for sequentially writing data received from the network to the first , second and third buffer memory means and for generating an interrupt signal when the first buffer memory means is full; a driver means for transferring data from the first, second and third memory means to a first, second and third portions of an application memory means, respectively, the driver means being actuated upon receiving the interrupt signal whereby data transfer from the first memory means to the first portion of the application memory means is performed while data is being written into the second buffer memory means; a plurality of receive descriptors, the plurality of receive descriptors being set up by the driver means to indicate descriptor ownership status and start of packet status, each receive descriptor being associated with one of the buffer memory means, the descriptor ownership status indicating whether the controller can write to the one of the buffer memory means associated with the receive descriptor, and the start of packet status indicating whether a data packet can begin in the one of the buffer memory means associated with the receive descriptor; wherein the controller polls the plurality of receive descriptors for receive descriptor that indicates ownership of the receive descriptor by the controller and start of packet status before the controller write data into the first, second or third buffer memory means; wherein the controller updates the receive descriptor to relinguish ownership of the receive descriptor and to change the start of packet status after the first, second or third buffer memory means is filled; wherein before beginning the transfer of data from the first, second or third buffer memory means to the first, second or third portion of the application memory means, respectively, the driver means polls for the updated receive descriptors; and wherein the controller performs a lookahead polling of a succeeding receive descriptor when a specified byte of the data packet is provided to the controller.
Claim 6
Dependent Claim
16 words
The system of claim 3 wherein the plurality of receive descriptors are in groups of three.
Claim 7
Dependent Claim
18 words
The system of claim 4 wherein the driver means accomplishes data transfer with the use of a pointer.
References Cited (Backward Citations)
US4032899A
Cited
US4075691A
Cited
US4493021A
Cited
US5105382A
Cited
US5163132A
Cited
US5339439A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-02 | 2000-01-01 | 2000-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-02 | 2004-01-01 | 2004-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-02 | 2008-01-01 | 2008-07-02 | $7700.00 | Window Closed / Lapsed |