US5532899A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Voltage protection structure for semiconductor devices
Assignee: NXP USA Inc
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Filing: 1994-03-21
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Granted: 1996-07-02
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Expires: 2014-03-21
Abstract
Abstract A voltage protection arrangement (10) comprises a semiconductor substrate (12) having at least two electrical conductors (16,18,20) adjacent an edge of the substrate. An aperture (22) extends from the edge towards a point between the two electrical conductors. The aperture (22) reduces conductance between the two electrical conductors (16,18) in a region adjacent the edge of the substrate (12), such that if an excess voltage occurs between the two conductors (16,18), a reduced current flows in the region.
Inventors
- 👤 Jean-Claude Tarbouriech
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:40
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
73 words
A voltage protection arrangement comprising: a semiconductor substrate having at least two discrete electrical conductors adjacent an edge of the substrate, and an aperture extending from said edge towards a point between the two electrical conductors, whereby the aperture reduces conductance between the two electrical conductors in a region adjacent the edge of the substrate, such that if an excess voltage occurs between the two conductors, a reduced current flows in the region.
Claim 2
Dependent Claim
73 words
A voltage protection arrangement comprising: a semiconductor substrate having at least two discrete electrical conductors adjacent an edge of the substrate, and an aperture extending from said edge towards a point between the two electrical conductors, whereby the aperture reduces conductance between the two electrical conductors in a region adjacent the edge of the substrate, such that if an excess voltage occurs between the two conductors, a reduced current flows in the region.
Claim 3
Dependent Claim
12 words
The arrangement of claim 1 wherein the semiconductor substrate comprises diffused silicon.
Claim 4
Dependent Claim
20 words
The arrangement of claim 1 wherein the two electrical conductors comprise a series of metal contacts deposited in the substrate.
Claim 5
Dependent Claim
85 words
The arrangement of claim 1 further comprising a polycrystalline transistor gate structure formed over the substrate, wherein the polycrystalline transistor gate structure is insulated from the substrate by an oxide layer, the gate structure extending to the edge of the substrate between the aperture and one of the two conductors, such that if an excess voltage occurs between the two conductors, the oxide layer is less susceptible to a breakdown causing a short circuit between the gate structure and the substrate because of the aperture.
Claim 6
Dependent Claim
100 words
A transistor device comprising: a semiconductor substrate; and at least two discrete electrical conductors formed over the semiconductor substrate, wherein the at least two discrete electrical conductors are adjacent an edge of the semiconductor substrate, and wherein the semiconductor substrate includes an aperture extending from the edge towards a point between the at least two discrete electrical conductors, whereby the aperture reduces conductance between the at least two electrical conductors in a region adjacent the edge such that when an excess voltage occurs between the at least two electrical conductors, a reduced current flows in the region adjacent the edge.
Claim 7
Dependent Claim
100 words
A transistor device comprising: a semiconductor substrate; and at least two discrete electrical conductors formed over the semiconductor substrate, wherein the at least two discrete electrical conductors are adjacent an edge of the semiconductor substrate, and wherein the semiconductor substrate includes an aperture extending from the edge towards a point between the at least two discrete electrical conductors, whereby the aperture reduces conductance between the at least two electrical conductors in a region adjacent the edge such that when an excess voltage occurs between the at least two electrical conductors, a reduced current flows in the region adjacent the edge.
Claim 8
Dependent Claim
12 words
The device of claim 5 wherein the semiconductor substrate comprises diffused silicon.
Claim 9
Dependent Claim
22 words
The device of claim 5 wherein the at least two electrical conductors comprise a series of metal contacts deposited onto the substrate.
Claim 10
Dependent Claim
91 words
The device of claim 5 further comprising a polycrystalline transistor gate structure formed over the semiconductor substrate, wherein the polycrystalline transistor gate structure is insulated from the semiconductor substrate by an oxide layer, and wherein the gate structure extends to the edge of the semiconductor substrate between the aperture and one of the two conductors, such that if an excess voltage occurs between the two conductors, the oxide layer is less susceptible to a breakdown causing a short circuit between the gate structure and the semiconductor substrate because of the aperture.
References Cited (Backward Citations)
GB925039A
Cited
GB1531811A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-02 | 2000-01-01 | 2000-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-02 | 2004-01-01 | 2004-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-02 | 2008-01-01 | 2008-07-02 | $7700.00 | Window Closed / Lapsed |