US5532716A
Expired / Lapsed
US
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Resolution conversion system
Assignee: Toshiba Corp
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Filing: 1992-12-09
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Granted: 1996-07-02
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Expires: 2012-12-09
Abstract
Abstract A memory storing image data at a m1×n1 (horizontal to vertical) dot resolution is read out at a horizontal scanning rate corresponding to a first clock signal at a frequency f 1 . Data read out from the memory is latched in a first storage device in response to the first clock signal. An output from the first storage device is latched in a second storage device in response to a second clock signal at a frequency f 2 . The rate f 2 is selected to be less than f 1 and to correspond to the desired display rate of the display device having a pixel resolution of m2×n2. f 1 and f 2 are related such that f 1 /f 2 =(m1/m2). The difference in frequencies causes some of the X address from the memory to be dropped and not stored in the second storage device thereby resulting in the desired data conversion in the X direction. The Y address is incremented by an amount equal to n1/n2 to affect the resolution conversion in the Y direction.
Inventors
- 👤 Yoshinobu Sano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 17:11
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G09G5/391
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
277 words
A resolution conversion system having a memory for storing data at a first predetermined resolution and a display device for displaying data at a second predetermined resolution different from the first predetermined resolution, said conversion system comprising: address generating means connected to said memory and generating an address for reading out the stored data in the memory; a first storage device connected to said memory and storing therein the data read out in response to the address from the address generating means, said first storage device outputting said stored data in response to a first clock signal having a frequency f 1 ; and a second storage device connected to said first storage device and said display device, and second storage device operating in response to a second clock signal having a frequency f 2 , different from the frequency f 1 of said first clock signal, for storing therein only selected data from the first storage device, said second storage device outputting the selected data stored therein to the display device, said first storage device having an output and said second storage device having an input connected to the output of said first storage device, and said second storage device selecting for storage therein only the data appearing on said input which is in synchronism with a rising edge of said second clock signal at said frequency f 2 , wherein the first predetermined resolution corresponds to a storage size within said memory of n1×m1, and said second predetermined resolution corresponds to a display size of said display device of n2×m2, and wherein f 1 and f 2 are related according to the formula: f.sub.2 =(m2/m1).f.sub.1.
Claim 2
Dependent Claim
277 words
A resolution conversion system having a memory for storing data at a first predetermined resolution and a display device for displaying data at a second predetermined resolution different from the first predetermined resolution, said conversion system comprising: address generating means connected to said memory and generating an address for reading out the stored data in the memory; a first storage device connected to said memory and storing therein the data read out in response to the address from the address generating means, said first storage device outputting said stored data in response to a first clock signal having a frequency f 1 ; and a second storage device connected to said first storage device and said display device, and second storage device operating in response to a second clock signal having a frequency f 2 , different from the frequency f 1 of said first clock signal, for storing therein only selected data from the first storage device, said second storage device outputting the selected data stored therein to the display device, said first storage device having an output and said second storage device having an input connected to the output of said first storage device, and said second storage device selecting for storage therein only the data appearing on said input which is in synchronism with a rising edge of said second clock signal at said frequency f 2 , wherein the first predetermined resolution corresponds to a storage size within said memory of n1×m1, and said second predetermined resolution corresponds to a display size of said display device of n2×m2, and wherein f 1 and f 2 are related according to the formula: f.sub.2 =(m2/m1).f.sub.1.
Claim 3
Dependent Claim
44 words
A resolution conversion system according to any one of claim 1 wherein the address generating means comprises a Y address generating circuit converting the first predetermined resolution of the memory to the second predetermined resolution of the display device in a vertical scanning direction.
Claim 4
Dependent Claim
81 words
A resolution conversion system according to claim 2, wherein the Y address generating circuit comprises: an increment register which stores the ratio of the vertical scanning resolution in the memory to the vertical scanning resolution in the display device; a Y address register storing a current Y address; an adder adding the address from the Y address register and the increment register; and means for feeding the output of the adder to the Y address register as a new current address.
Claim 5
Dependent Claim
42 words
A resolution conversion system according to claim 3, wherein said Y address register stores an integral part and a decimal part, and said conversion system further comprises means for feeding the integral part of said Y address register to said display device.
Claim 6
Dependent Claim
51 words
A resolution conversion system according to claim 1, wherein the ratio the frequency f 1 of the first clock signal to the frequency f 2 of the second clock signal corresponds to the ratio of the horizontal scanning resolution in the memory to the horizontal scanning resolution in the display device.
Claim 7
Independent Claim
127 words
A method of transmitting selected portions of data stored in a m1×n1 memory to a m2×n2 display device where m1, m2, n1, n2 are integers with m2<m1, comprising the steps of: addressing data stored in said memory, reading out data stored in said memory, storing said read out data from said memory into a first storage device, transmitting data from said first storage device to a second storage device at a first rate f 1 , storing data in said second storage device at a second rate f 2 less than said first rate f 1 thereby omitting the storage of some of the data transmitted from said first storage device, and selecting f 1 and f 2 such as to satisfy the relationship f.sub.1 /f.sub.2 =(m1/m2).
Claim 8
Independent Claim
127 words
A method of transmitting selected portions of data stored in a m1×n1 memory to a m2×n2 display device where m1, m2, n1, n2 are integers with m2<m1, comprising the steps of: addressing data stored in said memory, reading out data stored in said memory, storing said read out data from said memory into a first storage device, transmitting data from said first storage device to a second storage device at a first rate f 1 , storing data in said second storage device at a second rate f 2 less than said first rate f 1 thereby omitting the storage of some of the data transmitted from said first storage device, and selecting f 1 and f 2 such as to satisfy the relationship f.sub.1 /f.sub.2 =(m1/m2).
Claim 9
Dependent Claim
86 words
The method as recited in claim 6 further comprising the steps of: generating X addresses in sequential order to select X addresses of said data stored in said memory, generating Y addresses by selecting a reduced number of Y addresses of said data stored in said memory, said Y address generating including incrementing a given Y address utilizing the ratio n1/n2, where n2<n1, to obtain a new Y address, thereby omitting the generation of some of the Y addresses of said data stored in said memory.
Claim 10
Independent Claim
145 words
A method of transmitting selected portions of data stored in a m1×n1 memory to a m2×n2 display device where m1, m2, n1, n2 are integers with m2<m1, comprising the steps of: addressing data stored in said memory, reading out data stored in said memory, storing said read out data from said memory into a first storage device, transmitting data from said first storage device to a second storage device in response to a first clock signal having a first frequency f 1 , storing data in said second storage device in synchronism with a second clock signal having a second frequency f 2 less than the frequency f 1 of said first clock signal thereby omitting the storage of some of the data transmitted from said first storage device, and selecting f 1 and f 2 such as to satisfy the relationship f.sub.1 /f.sub.2 =(m1/m2).
Claim 11
Independent Claim
145 words
A method of transmitting selected portions of data stored in a m1×n1 memory to a m2×n2 display device where m1, m2, n1, n2 are integers with m2<m1, comprising the steps of: addressing data stored in said memory, reading out data stored in said memory, storing said read out data from said memory into a first storage device, transmitting data from said first storage device to a second storage device in response to a first clock signal having a first frequency f 1 , storing data in said second storage device in synchronism with a second clock signal having a second frequency f 2 less than the frequency f 1 of said first clock signal thereby omitting the storage of some of the data transmitted from said first storage device, and selecting f 1 and f 2 such as to satisfy the relationship f.sub.1 /f.sub.2 =(m1/m2).
Claim 12
Dependent Claim
86 words
The method as recited in claim 8 further comprising the steps of: generating X addresses in sequential order to select X addresses of said data stored in said memory, generating Y addresses by selecting a reduced number of Y addresses of said data stored in said memory, said Y address generating including incrementing a given Y address utilizing the ratio n1/n2, where n2<n1, to obtain a new Y address, thereby omitting the generation of some of the Y addresses of said data stored in said memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-02 | 2000-01-01 | 2000-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-02 | 2004-01-01 | 2004-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-02 | 2008-01-01 | 2008-07-02 | $7700.00 | Window Closed / Lapsed |