Error detection method using convolutional code and viterbi decoding

Claim 2

An error detection method for detecting an error in transmission data, the transmission data being obtained by adding error detection codes to input data to convert the input data into encoded data having a predetermined number of bits and then subjecting the encoded data as information bits to an error correction coding operation using convolutional code, said method comprising steps of: dividing the transmission data into a plurality of error detection blocks each of which includes consecutive received signal train elements in Viterbi decoding, the consecutive received signal train elements having a smaller number of bits than the predetermined number of bits; subjecting the transmission data and the consecutive received signal train elements in each error detection block to an error correction Viterbi decoding operation to obtain predetermined parameters for an error detection using metrics, the metrics including one of branch metrics for the consecutive received signal train elements in each error detection block, and path metrics through add-compare-select operation for each state; storing the obtained predetermined parameters; decoding the error detection codes in the transmission data after said error correction Viterbi decoding operation, and then detecting using the decoded error detection codes whether or not there is an error in the transmission data after said error correction Viterbi decoding operation; detecting, using the stored predetermined parameters, whether or not there is an error in the consecutive received signal train elements in each error detection block, when an error in the transmission data after said error correction Viterbi decoding operation is detected.

Claim 3

An error detection method as set forth in claim 1, wherein the predetermined parameters include a partial path metric for each error detection block of a finally survived path in said Viterbi decoding.

Claim 4

An error detection method as set forth in claim 1, wherein the predetermined parameters include at least one of maximum and minimum values of path metrics of a finally received signal train in each error detection block for each state and a difference between the maximum and minimum values.

Claim 5

An error detection method as set forth in claim 1, wherein the predetermined parameters include a partial path metric for each error detection block of a finally survived path in said Viterbi decoding, and include at least one of maximum and minimum values of the path metrics of a finally received signal train in each error detection block for each state and a difference between the maximum and minimum values.

Claim 6

An error detection method as set forth in claim 1, wherein the predetermined parameters include a path metric of a finally survived path in said Viterbi decoding.

Claim 7

An error correction and detection decoder for detecting an error in transmission data, the transmission data being obtained by adding error detection codes to input data to convert the input data into encoded data having a predetermined number of bits and then subjecting the encoded data as information bits to an error correction coding operation using convolutional code, said decoder comprising: an error correction decoder circuit for dividing the transmission data into a plurality of error detection blocks each of which includes consecutive received signal train elements in Viterbi decoding, and for subjecting the transmission data and the consecutive received signal train elements in each error detecting block to an error correction Viterbi decoding operation to obtain predetermined parameters for an error detection using metrics, the consecutive received signal train elements having a smaller number of bits than the predetermined number of bits; a memory circuit for storing the obtained predetermined parameters; an error detection decoding circuit for decoding the error detection codes which are included in the transmission data after the error correction Viterbi decoding operation, for detecting, using the decoded error detection codes, whether or not there is an error in the transmission data after the error correction Viterbi decoding operation, and for outputting an error detection flag for indicating whether or not there is an error in the transmission data after the error correction Viterbi decoding operation; a metric error detection circuit for taking in the error detection flag from said error detection decoding circuit and the predetermined parameters from said memory circuit, for detecting, using the predetermined parameters, whether or not there is an error in the consecutive received signal train elements in each error detection block, and for outputting block error detection flags each of which indicates whether or not there is an error in the consecutive received signal train elements in each error detection block, when the error detection flag indicates that an error in the transmission data after the error correction Viterbi decoding operation has been detected.

Claim 8

An error correction and detection decoder for detecting an error in transmission data, the transmission data being obtained by adding error detection codes to input data to convert the input data into encoded data having a predetermined number of bits and then subjecting the encoded data as information bits to an error correction coding operation using convolutional code, said decoder comprising: an error correction decoder circuit for dividing the transmission data into a plurality of error detection blocks each of which includes consecutive received signal train elements in Viterbi decoding, and for subjecting the transmission data and the consecutive received signal train elements in each error detecting block to an error correction Viterbi decoding operation to obtain predetermined parameters for an error detection using metrics, the consecutive received signal train elements having a smaller number of bits than the predetermined number of bits; a memory circuit for storing the obtained predetermined parameters; an error detection decoding circuit for decoding the error detection codes which are included in the transmission data after the error correction Viterbi decoding operation, for detecting, using the decoded error detection codes, whether or not there is an error in the transmission data after the error correction Viterbi decoding operation, and for outputting an error detection flag for indicating whether or not there is an error in the transmission data after the error correction Viterbi decoding operation; a metric error detection circuit for taking in the error detection flag from said error detection decoding circuit and the predetermined parameters from said memory circuit, for detecting, using the predetermined parameters, whether or not there is an error in the consecutive received signal train elements in each error detection block, and for outputting block error detection flags each of which indicates whether or not there is an error in the consecutive received signal train elements in each error detection block, when the error detection flag indicates that an error in the transmission data after the error correction Viterbi decoding operation has been detected.

Claim 9

An error correction and detection decoder for detecting an error in transmission data, the transmission data being obtained by adding error detection codes to input data to convert the input data into encoded data having a predetermined number of bits and then subjecting the encoded data as information bits to an error correction coding operation using convolutional code, said decoder comprising: error correction decoder means for dividing the transmission data into a plurality of error detection blocks each of which includes consecutive received signal train elements in Viterbi decoding, and for subjecting the transmission data and the consecutive received signal train elements in each error detecting block to an error correction Viterbi decoding operation to obtain predetermined parameters for an error detection using metrics, the consecutive received signal train elements having a smaller number of bits than the predetermined number of bits; memory means for storing the obtained predetermined parameters; error detection decoding means for decoding the error detection codes which are included in the transmission data after the error correction Viterbi decoding operation, for detecting, using the decoded error detection codes, whether or not there is an error in the transmission data after the error correction Viterbi decoding operation, and for outputting an error detection flag for indicating whether or not there is an error in the transmission data after the error correction Viterbi decoding operation; metric error detection means for taking in the error detection flag from said error detection decoding means and the predetermined parameters from said memory means, for detecting, using the predetermined parameters, whether or not there is an error in the consecutive received signal train elements in each error detection block, and for outputting block error detection flags each of which indicates whether or not there is an error in the consecutive received signal train elements in each error detection block, when the error detection flag indicates that an error in the transmission data after the error correction Viterbi decoding operation has been detected.

Claim 10

An error correction and detection decoder for detecting an error in transmission data, the transmission data being obtained by adding error detection codes to input data to convert the input data into encoded data having a predetermined number of bits and then subjecting the encoded data as information bits to an error correction coding operation using convolutional code, said decoder comprising: error correction decoder means for dividing the transmission data into a plurality of error detection blocks each of which includes consecutive received signal train elements in Viterbi decoding, and for subjecting the transmission data and the consecutive received signal train elements in each error detecting block to an error correction Viterbi decoding operation to obtain predetermined parameters for an error detection using metrics, the consecutive received signal train elements having a smaller number of bits than the predetermined number of bits; memory means for storing the obtained predetermined parameters; error detection decoding means for decoding the error detection codes which are included in the transmission data after the error correction Viterbi decoding operation, for detecting, using the decoded error detection codes, whether or not there is an error in the transmission data after the error correction Viterbi decoding operation, and for outputting an error detection flag for indicating whether or not there is an error in the transmission data after the error correction Viterbi decoding operation; metric error detection means for taking in the error detection flag from said error detection decoding means and the predetermined parameters from said memory means, for detecting, using the predetermined parameters, whether or not there is an error in the consecutive received signal train elements in each error detection block, and for outputting block error detection flags each of which indicates whether or not there is an error in the consecutive received signal train elements in each error detection block, when the error detection flag indicates that an error in the transmission data after the error correction Viterbi decoding operation has been detected.

Claim 11

The error correction and detection decoder according to claim 7, wherein said error detection decoding means is further for outputting decoded data.

Claim 12

The error correction and detection decoder according to claim 7, wherein the error detection flag output by said error detection decoding means comprises a CRC error detection flag.

Claim 13

The error correction and detection decoder according to claim 7, wherein the predetermined parameters include a partial path metric for each error detection block of a finally survived path in said Viterbi decoding.

Claim 14

The error correction and detection decoder according to claim 7, wherein the predetermined parameters include at least one of maximum and minimum values of path metrics of a finally received signal train in each error detection block for each state and a difference between the maximum and minimum values.

Claim 15

The error correction and detection decoder according to claim 7, wherein the predetermined parameters include a partial path metric for each error detection block of a finally survived path in said Viterbi decoding, and include at least one of maximum and minimum values of the path metrics of a finally received signal train in each error detection block for each state and a difference between the maximum and minimum values.

Claim 16

The error correction and detection decoder according to claim 7, wherein the predetermined parameters include a path metric of a finally survived path in said Viterbi decoding.