Partitioned display apparatus

Claim 1

A partitioned display apparatus for displaying video information received from a plurality of memory devices, each memory device organized as 2 x rows by 2 y columns of memory locations and a plurality of bits deep, where x and y are integers, said display apparatus comprising: a plurality of memory means for storing data representing at least one pixel slice array coupled to a digital video input; a fault-tolerant cross bar routing switch means coupled to the plurality of memory devices for switching a video output representing the at least one pixel slice array from the plurality of memory means to a VRAM matrix configured to match said pixel slice array; a graphical image source memory subsystem controller coupled to the plurality of memory devices and the video output from the cross bar routing switch means so that the video input, the pixel slice array, a plurality of addressing data, and a plurallity of control signals cooperate to produce a rapidly updated high resolution image on a visual display means, wherein the visual display means comprises a plurality of display slices, each display slice including a plurality of pixels, at least one of the display slices organized as 2 n rows by 2 m columns of pixels as a function of the memory means, where n and m are integers; and means for receiving the video information from the plurality of memory devices and driving at least a portion of said plurality of pixels of said each display device in parallel.