Method and apparatus for converting floating-point pixel values to byte pixel values by table lookup

Claim 2

Image display apparatus, comprising: pixel value memory means having a plurality of memory locations for storing words of data, each of said words of data comprising a predetermined standard representation of a Z-bit floating-point value that specifies an image pixel, said Z-bit floating-point value including at least an N-bit exponent portion and an M-bit mantissa portion, said N-bit exponent portion and a most significant portion of said M-bit mantissa portion being stored in a most significant half-word of each of said words and a least significant portion of said M-bit mantissa portion being stored in a least significant half word of each of said words; a look-up table memory comprised of a plurality of address input signal lines and a plurality of data output signal lines, said look-up table memory being further comprised of a plurality of storage locations individual ones of which store an X-bit pixel value in integer form, individual ones of said plurality of storage locations being selectively addressable by an address applied to said plurality of address input signal lines, wherein said plurality of address signal lines are coupled to an output of said pixel value memory means for receiving only most significant half words from said pixel value memory means, wherein N individual ones of said plurality of address signal lines are coupled to N bits of said N-bit exponent portion of a most significant half word, wherein Y individual ones of said plurality of address signal lines are coupled to Y most significant bits (MSBs) of said most significant M-bit mantissa portion of the most significant half word, wherein Y is less than M, and wherein X is less than (N+Y); and display means, having an input coupled to said plurality of data output signal lines, for storing X-bit pixel values output from said look-up table memory and for displaying individual ones of said pixels in accordance with information that is specified by said X-bit integer pixel value.

Claim 3

Image display apparatus as set forth in claim 1, wherein individual ones of said pixel values are processed prior to storage in said look-up table memory so as perform one or more of the operations of gamma correction, scaling, and range limiting.

Claim 4

Image display apparatus as set forth in claim 1, wherein Z equals 32, wherein N equals eight, wherein Y equals seven, and wherein X equals eight.

Claim 5

Image display apparatus as set forth in claim 1, wherein said Z-bit floating-point value further includes a sign bit, and wherein one of said plurality of address signal lines is coupled to said sign bit.

Claim 6

Image display apparatus, comprising: pixel value memory means having a plurality of memory locations for storing words of data, each of said words of data comprising a predetermined standard representation of a Z-bit floating-point value that specifies an image pixel, said Z-bit floating-point value including at least an N-bit exponent portion and an M-bit mantissa portion, said N-bit exponent portion and a most significant portion of said M-bit mantissa portion being stored in a most significant half-word of each of said words and a least significant portion of said M-bit mantissa portion being stored in a least significant half word of each of said words; a plurality of look-up table memories individual ones of which are each comprised of a plurality of address input signal lines and a plurality of data output signal lines, each of said plurality of look-up table memories being further comprised of a plurality of X-bit storage locations individual ones of which store a component of a pixel value in integer form, individual ones of said plurality of storage locations being selectively addressable by an address applied to said plurality of address input signal lines, wherein said plurality of address signal lines of each of said plurality of look-up table memories are coupled to an output of said pixel value memory means for receiving only most significant half words from said pixel value memory means, wherein N individual ones of said plurality of address signal lines are coupled to N bits of said N-bit exponent portion of a most significant half word, wherein Y individual ones of said plurality of address signal lines are coupled to Y most significant bits (MSBs) of said M-bit mantissa portion of the most significant half word, wherein Y is less than M, and wherein X is less than (N+Y); and display means, having an input coupled to said plurality of data output signal lines of each of said plurality of look-up table memories, for storing X-bit pixel values output from each of said plurality of look-up table memories and for displaying individual ones of said pixels in accordance with information that is specified by said X-bit integer pixel values.

Claim 7

Image display apparatus, comprising: pixel value memory means having a plurality of memory locations for storing words of data, each of said words of data comprising a predetermined standard representation of a Z-bit floating-point value that specifies an image pixel, said Z-bit floating-point value including at least an N-bit exponent portion and an M-bit mantissa portion, said N-bit exponent portion and a most significant portion of said M-bit mantissa portion being stored in a most significant half-word of each of said words and a least significant portion of said M-bit mantissa portion being stored in a least significant half word of each of said words; a plurality of look-up table memories individual ones of which are each comprised of a plurality of address input signal lines and a plurality of data output signal lines, each of said plurality of look-up table memories being further comprised of a plurality of X-bit storage locations individual ones of which store a component of a pixel value in integer form, individual ones of said plurality of storage locations being selectively addressable by an address applied to said plurality of address input signal lines, wherein said plurality of address signal lines of each of said plurality of look-up table memories are coupled to an output of said pixel value memory means for receiving only most significant half words from said pixel value memory means, wherein N individual ones of said plurality of address signal lines are coupled to N bits of said N-bit exponent portion of a most significant half word, wherein Y individual ones of said plurality of address signal lines are coupled to Y most significant bits (MSBs) of said M-bit mantissa portion of the most significant half word, wherein Y is less than M, and wherein X is less than (N+Y); and display means, having an input coupled to said plurality of data output signal lines of each of said plurality of look-up table memories, for storing X-bit pixel values output from each of said plurality of look-up table memories and for displaying individual ones of said pixels in accordance with information that is specified by said X-bit integer pixel values.

Claim 8

Image display apparatus as set forth in claim 5 wherein said component is a color.

Claim 9

Image display apparatus as set forth in claim 5, wherein individual ones of said pixel values are processed prior to storage in said plurality of look-up table memories so as perform one or more of the operations of gamma correction, scaling, and range limiting.

Claim 10

Image display apparatus as set forth in claim 5, wherein Z equals 32, wherein N equals eight, wherein Y equals seven, and wherein X equals eight.

Claim 11

Image display apparatus as set forth in claim 5, wherein said Z-bit floating-point value further includes a sign bit, and wherein one of said plurality of address signal lines of each of said plurality of look-up table memories is coupled to said sign bit.

Claim 14

A method as set forth in claim 10, and further comprising a step of processing individual ones of the pixel values prior to storage in the look-up table memory so as perform one or more of the operations of gamma correction, scaling, and range limiting.

Claim 15

A method as set forth in claim 10, wherein Z equals 32, wherein N equals eight, wherein Y equals seven, and wherein X equals eight.

Claim 16

A method as set forth in claim 10, wherein the Z-bit floating-point value further includes a sign bit, and wherein the step of applying applies the sign bit to one of the plurality of address signal lines.