US5528604A
Expired / Lapsed
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Test pattern generation for an electronic circuit using a transformed circuit description
Assignee: Carnegie Mellon University
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Filing: 1995-01-18
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Granted: 1996-06-18
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Expires: 2015-01-18
Abstract
Abstract Test pattern generation for a sequential logic circuit having combinational logic elements and sequential elements (D flip-flops) is enhanced in generation time and test pattern quality by first transforming the circuit to simplify the circuit for test pattern generation. In one embodiment the retiming transformation is used in which sequential elements are moved across combinational logic elements to increase the ratio of the total number of states which are traversable, and thus simplify the circuit for test pattern generation. The test set generated is equally applicable to the transformed test circuit as well as the manufactured circuit.
Inventors
- 👤 Aiman H. El-Maleh
- 👤 Wojciech P. Maly
- 👤 Thomas E. Marchok
- 👤 Janusz E. Rajski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 23:42
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318392
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
65 words
A method of test pattern generation for a sequential logic circuit by using a modified version at the circuit, said method including a) transforming an original sequential logic circuit to a modified circuit while preserving the testability of a test set, and b) generating a test pattern for said modified circuit which can then be used with said original sequential logic circuit to detect faults.
Claim 2
Independent Claim
65 words
A method of test pattern generation for a sequential logic circuit by using a modified version at the circuit, said method including a) transforming an original sequential logic circuit to a modified circuit while preserving the testability of a test set, and b) generating a test pattern for said modified circuit which can then be used with said original sequential logic circuit to detect faults.
Claim 3
Dependent Claim
21 words
The method as defined by claim 1 wherein said modified circuit has fewer sequential elements than said original sequential logic circuit.
Claim 4
Dependent Claim
18 words
The method as defined by claim 1 wherein said step of transforming includes application of a retiming transform.
Claim 5
Dependent Claim
45 words
The method as defined by claim 3 wherein said original sequential logic circuit includes a plurality of combinational logic gates interconnected by a plurality of sequential elements, said step of retiming including moving sequential elements across combinational elements to reduce the number of sequential elements.
Claim 6
Dependent Claim
60 words
Apparatus for test pattern generation for a sequential logic circuit, said apparatus including: a) means for transforming an original sequential logic circuit to a modified circuit while preserving the testability of a test set, and b) means for generating a test pattern for said modified circuit which can then be used with said original sequential logic circuit to identify faults.
Claim 7
Dependent Claim
60 words
Apparatus for test pattern generation for a sequential logic circuit, said apparatus including: a) means for transforming an original sequential logic circuit to a modified circuit while preserving the testability of a test set, and b) means for generating a test pattern for said modified circuit which can then be used with said original sequential logic circuit to identify faults.
Claim 8
Dependent Claim
19 words
Apparatus as defined by claim 5 wherein said test circuit has fewer sequential elements than said sequential logic circuit.
Claim 9
Dependent Claim
19 words
Apparatus as defined by claim 5 wherein said means for transforming includes means for application of a retiming transform.
Claim 10
Dependent Claim
46 words
Apparatus as defined by claim 7 wherein said original sequential logic circuit includes a plurality of combinational logic gates interconnected by a plurality of sequential elements, said means for transforming including means for moving sequential elements across combinational elements to reduce the number of sequential elements.
References Cited (Backward Citations)
US5272390A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-18 | 1999-12-18 | 2000-06-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-18 | 2003-12-18 | 2004-06-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-18 | 2007-12-18 | 2008-06-18 | $7700.00 | Window Closed / Lapsed |