US5528187A
Expired / Lapsed
US
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Clock synchronizing circuit
Assignee: Sony Corp
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Filing: 1994-04-19
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Granted: 1996-06-18
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Expires: 2014-04-19
Abstract
Abstract Clock signals of the same phase are formed even when signal delays occur in clock signals transmitted on a clock line. In a clock synchronizing circuit which synchronizes circuit elements using clock signals taken from a common clock line, the clock line is bent midway into a pair of clock lines, and a center phase signal generating means generates a clock signal having a phase which is in the center of two clock signals of differing phase obtained from arbitrary points on the pair of clock lines which are at equal distances from the point at which the clock line is bent over. By using pairs of clock signals of differing phases taken at equal distances from the bend over point, three clock signals all having equal phase are obtained.
Inventors
- 👤 Hiroshi Sato
- 👤 Katsunori Seno
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 06:16
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/087; G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; H03K; H03K5/00; H03K5/15; H03K5/15013; H03K5/1506; H03K5/1508; H04; H04L; H04L7/00; H04L7/0008
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
90 words
A clock synchronizing circuit which synchronizes circuit elements using clock signals taken from a common clock line, with said clock line being bent midway to form a pair of clock lines, comprising: center phase signal generating means for generating a clock signal having a phase which is midway between respective phases of two clock signals of differring phase, said two clock signals having been taken from arbitrary points on said pair of clock lines at equal distances from the point at which said pair of clock lines are bent over.
Claim 2
Dependent Claim
90 words
A clock synchronizing circuit which synchronizes circuit elements using clock signals taken from a common clock line, with said clock line being bent midway to form a pair of clock lines, comprising: center phase signal generating means for generating a clock signal having a phase which is midway between respective phases of two clock signals of differring phase, said two clock signals having been taken from arbitrary points on said pair of clock lines at equal distances from the point at which said pair of clock lines are bent over.
Claim 3
Dependent Claim
58 words
A clock synchronizing circuit according to claim 1, said center phase signal generating means comprising: a first integrator; a second integrator, and a comparator which compares voltages outputted by both integrators, wherein a clock signal of a prescribed duty ratio is outputted when the voltage outputted from one integrator is higher than the voltage outputted from the other.
Claim 4
Dependent Claim
74 words
A clock synchronizing circuit according to claim 2, each of said integrators including: a d.c. component detector circuit set up at an output terminal of said integrator; an inverting amplifier for providing amplification and for reversing an phase of the output from the d.c. component detector and; a feedback path from an output of said inverting amplifier to an input of said integrator, wherein a clock signal of an arbitrary duty ratio is generated.
Claim 5
Dependent Claim
129 words
A clock synchronizing circuit which synchronizes circuit elements using clock signals taken from a common clock line, with said clock line being bent midway to form a pair of clock lines, comprising: center phase signal generating means for generating a clock signal having a phase which is midway between respective phases of two clock signals of differring phase, said two clock signals having been taken from arbitrary points on said pair of clock lines at equal distances from the point at which said pair of clock lines are bent over; and a PLL set up between said center phase signal generating means and said clock line, for adjusting the phase of the clock signal outputted from said center phase signal generating means to the phase of an external clock.
Claim 6
Dependent Claim
129 words
A clock synchronizing circuit which synchronizes circuit elements using clock signals taken from a common clock line, with said clock line being bent midway to form a pair of clock lines, comprising: center phase signal generating means for generating a clock signal having a phase which is midway between respective phases of two clock signals of differring phase, said two clock signals having been taken from arbitrary points on said pair of clock lines at equal distances from the point at which said pair of clock lines are bent over; and a PLL set up between said center phase signal generating means and said clock line, for adjusting the phase of the clock signal outputted from said center phase signal generating means to the phase of an external clock.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-18 | 1999-12-18 | 2000-06-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-18 | 2003-12-18 | 2004-06-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-18 | 2007-12-18 | 2008-06-18 | $7700.00 | Window Closed / Lapsed |