US5525528A
Expired / Lapsed
US
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Ferroelectric capacitor renewal method
Assignee: Ramtron International Corp
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Filing: 1994-02-23
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Granted: 1996-06-11
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Expires: 2014-02-23
Abstract
Abstract Ferroelectric capacitors in an integrated memory are renewed to improve retention performance. The renewal method is performed on a wafer containing ferroelectric memory die. In one method, a rejuvenation anneal is performed after all electrical tests, including those at elevated temperatures, have been accomplished, but before the failed die have been inked. The rejuvenation anneal is performed at or above the Curie temperature of the ferroelectric material. In the preferred embodiment, the ferroelectric material is PZT, and the rejuvenation anneal is a thermal treatment at 400° Centigrade in a nitrogen flow of roughly ten liters per minute for about an hour. In another method, separate electrical cycling and depoling operations are performed to provide the equivalent benefits of the single rejuvenation anneal. The electrical cycling operation is accomplished by writing about one hundred cycles at five volts alternating logic states into each ferroelectric capacitor into the array. The electrical cycling operation restores the symmetry and location of the hysteresis loop. The ferroelectric capacitor is then returned to the virgin state by a depoling operation. The electrical depoling operation is achieved by writing each capacitor in the array to a logic one and a logic zero at the full five volt power supply level initially, and then repeating each write cycle at decreasing power supply levels. The writing cycles are continued until the power supply is reduced to a minimum functional level and the polarization on the capacitors has been substantially removed.
Inventors
- 👤 Stanley Perino
- 👤 Sanjay Mitra
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:59
CPC Classifications
H; H10; H10B; H10B53/00; H10B53/30
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
128 words
A method of manufacturing ferroelectric memories comprising the steps of: fabricating a plurality of ferroelectric memory integrated circuits on a wafer; thermally treating the wafer at a first temperature less than the Curie temperature of the ferroelectric material in the memory circuits sufficiently to cause imprint degradation; electrically testing the memory circuits to identify bad die that have failed the electrical test and good die that have passed the electrical test; and annealing the wafer at a second temperature equal to or greater than the Curie temperature of the ferroelectric material in the memory circuits to restore a virgin state of polarization in the ferroelectric capacitors so that the imprint degradation caused by thermally treating the wafer at the first temperature is minimized and retention performance is improved.
Claim 2
Independent Claim
128 words
A method of manufacturing ferroelectric memories comprising the steps of: fabricating a plurality of ferroelectric memory integrated circuits on a wafer; thermally treating the wafer at a first temperature less than the Curie temperature of the ferroelectric material in the memory circuits sufficiently to cause imprint degradation; electrically testing the memory circuits to identify bad die that have failed the electrical test and good die that have passed the electrical test; and annealing the wafer at a second temperature equal to or greater than the Curie temperature of the ferroelectric material in the memory circuits to restore a virgin state of polarization in the ferroelectric capacitors so that the imprint degradation caused by thermally treating the wafer at the first temperature is minimized and retention performance is improved.
Claim 3
Dependent Claim
26 words
The method of claim 1 in which the annealing step further comprises the step of exposing the wafer to a nitrogen flow for about an hour.
Claim 4
Dependent Claim
24 words
The method of claim 1 in which the annealing step is conducted in a nitrogen flow of about ten liters of nitrogen per minute.
Claim 5
Dependent Claim
28 words
The method of claim 1 in which the fabricating step comprising the step of fabricating a plurality of non-volatile PZT ferroelectric memory integrated circuits on a silicon wafer.
Claim 6
Dependent Claim
19 words
The method of claim 4 in which the annealing step is conducted at a temperature of about 400° C.
Claim 7
Dependent Claim
43 words
The method of claim 1 in which the electrical testing step comprises the steps of: reading a first data state stored in the ferroelectric capacitors in the memory integrated circuit; and subsequently reading a second data state opposite to the first data state.
Claim 8
Dependent Claim
14 words
The method of claim 1 further comprising the steps of inking the bad die.
Claim 9
Dependent Claim
21 words
The method of claim 7 further comprising the steps of: creating individual die from the wafer; and packaging the good die.
Claim 10
Dependent Claim
25 words
The method of claim 8 in which the step of packaging the good die comprises the step of packaging the good die in plastic packages.
Claim 11
Dependent Claim
36 words
The method of claim 1 in which the fabricating step includes the step of creating a ferroelectric capacitor stack and associated electrical interconnection of sufficient mechanical and thermal integrity to withstand the annealing step without damage.
Claim 12
Dependent Claim
50 words
A manufacturing method for an integrated circuit PZT ferroelectric memory that is performed on a wafer including a plurality of the ferroelectric memories, the method comprising the step of annealing the wafer at about 400° C. in a nitrogen flow of about ten liters per minute for about an hour.
Claim 13
Dependent Claim
50 words
A manufacturing method for an integrated circuit PZT ferroelectric memory that is performed on a wafer including a plurality of the ferroelectric memories, the method comprising the step of annealing the wafer at about 400° C. in a nitrogen flow of about ten liters per minute for about an hour.
Claim 14
Dependent Claim
125 words
A renewal method for imprinted ferroelectric capacitors in an integrated circuit memory comprising the steps of: fabricating a plurality of ferroelectric memory integrated circuits on a silicon wafer; thermally treating the wafer at a first temperature less than the Curie temperature of the ferroelectric material in the memory circuits; electrically testing the memory circuits at the wafer level to identify bad die that have failed the electrical test and good die that have passed the electrical test; electrically cycling the memory circuits; and electrically depoling the memory circuits to restore a virgin state in the ferroelectric capacitors, wherein the electrical depoling step comprises the step of writing opposite data states into each of the ferroelectric capacitors in the memory circuits at sequentially decreasing voltage levels.
Claim 15
Dependent Claim
125 words
A renewal method for imprinted ferroelectric capacitors in an integrated circuit memory comprising the steps of: fabricating a plurality of ferroelectric memory integrated circuits on a silicon wafer; thermally treating the wafer at a first temperature less than the Curie temperature of the ferroelectric material in the memory circuits; electrically testing the memory circuits at the wafer level to identify bad die that have failed the electrical test and good die that have passed the electrical test; electrically cycling the memory circuits; and electrically depoling the memory circuits to restore a virgin state in the ferroelectric capacitors, wherein the electrical depoling step comprises the step of writing opposite data states into each of the ferroelectric capacitors in the memory circuits at sequentially decreasing voltage levels.
Claim 16
Dependent Claim
30 words
The method of claim 12 in which the electrical cycling step comprises the step of repetitively alternating opposite data states into each of the ferroelectric capacitors in the memory circuits.
Claim 17
Dependent Claim
41 words
The method of claim 12 in which the electrical cycling step is accomplished by writing about one hundred cycles of alternating opposite data states into each of the ferroelectric capacitors in the memory circuits at a full power supply voltage level.
Claim 18
Dependent Claim
43 words
The method of claim 12 in which the electrical testing step comprises the steps of: reading a first data state stored in the ferroelectric capacitors in the memory integrated circuit; and subsequently reading a second data state opposite to the first data state.
Claim 19
Dependent Claim
14 words
The method of claim 12 further comprising the steps of inking the bad die.
Claim 20
Dependent Claim
21 words
The method of claim 16 further comprising the steps of: creating individual die from the wafer; and packaging the good die.
Claim 21
Dependent Claim
25 words
The method of claim 17 in which the step of packaging the good die comprises the step of packaging the good die in plastic packages.
Claim 22
Dependent Claim
123 words
A renewal method for an integrated circuit ferroelectric memory performed on a wafer including a plurality of memory circuits, wherein each memory circuit includes a plurality of ferroelectric capacitors, the method comprising the steps of: electrically cycling the memory circuits; and subsequently electrically depoling the memory circuits, wherein the electrical depoling step comprises the steps of: (a) writing opposite data states into each of the ferroelectric capacitors in the memory circuit at a full power supply voltage level; (b) subsequently reducing the writing voltage; (c) subsequently writing opposite data states into each of the ferroelectric capacitors in the memory circuit at the reduced voltage; and (d) repeating steps (b) and (c) until the writing voltage has been reduced to a minimum voltage level.
Claim 23
Dependent Claim
123 words
A renewal method for an integrated circuit ferroelectric memory performed on a wafer including a plurality of memory circuits, wherein each memory circuit includes a plurality of ferroelectric capacitors, the method comprising the steps of: electrically cycling the memory circuits; and subsequently electrically depoling the memory circuits, wherein the electrical depoling step comprises the steps of: (a) writing opposite data states into each of the ferroelectric capacitors in the memory circuit at a full power supply voltage level; (b) subsequently reducing the writing voltage; (c) subsequently writing opposite data states into each of the ferroelectric capacitors in the memory circuit at the reduced voltage; and (d) repeating steps (b) and (c) until the writing voltage has been reduced to a minimum voltage level.
Claim 24
Dependent Claim
26 words
The method of claim 19 in which the step of reducing the writing voltage comprises the step of reducing the writing voltage by an incremental voltage.
Claim 25
Dependent Claim
122 words
A renewal method for avoiding imprinting of ferroelectric capacitors in an integrated circuit memory comprising the steps of: fabricating a plurality of ferroelectric memory integrated circuits on a silicon wafer; thermally treating the wafer at a first temperature less than the Curie temperature of the ferroelectric material in the memory circuits; electrically testing the memory circuits at the wafer level to identify bad die that have failed the electrical test and good die that have passed the electrical test; and electrically depoling the memory circuits to restore a virgin state in the ferroelectric capacitors, wherein the electrical depoling step comprises the step of writing opposite data states into each of the ferroelectric capacitors in the memory circuits at sequentially decreasing voltage levels.
Claim 26
Dependent Claim
122 words
A renewal method for avoiding imprinting of ferroelectric capacitors in an integrated circuit memory comprising the steps of: fabricating a plurality of ferroelectric memory integrated circuits on a silicon wafer; thermally treating the wafer at a first temperature less than the Curie temperature of the ferroelectric material in the memory circuits; electrically testing the memory circuits at the wafer level to identify bad die that have failed the electrical test and good die that have passed the electrical test; and electrically depoling the memory circuits to restore a virgin state in the ferroelectric capacitors, wherein the electrical depoling step comprises the step of writing opposite data states into each of the ferroelectric capacitors in the memory circuits at sequentially decreasing voltage levels.
Claim 27
Dependent Claim
14 words
The method of claim 21 further comprising the steps of inking the bad die.
Claim 28
Dependent Claim
21 words
The method of claim 22 further comprising the steps of: creating individual die from the wafer; and packaging the good die.
Claim 29
Dependent Claim
25 words
The method of claim 23 in which the step of packaging the good die comprises the step of packaging the good die in plastic packages.
Claim 30
Dependent Claim
175 words
A renewal method for imprinted ferroelectric capacitors in an integrated circuit memory comprising the steps of: fabricating a plurality of ferroelectric memory integrated circuits on a silicon wafer; thermally treating the wafer at a first temperature less than the Curie temperature of the ferroelectric material in the memory circuits; electrically testing the memory circuits at the wafer level to identify bad die that have failed the electrical test and good die that have passed the electrical test; electrically cycling the memory circuits; and electrically depoling the memory circuits to restore a virgin state in the ferroelectric capacitors, wherein the electrical depoling step comprises the steps of: (a) writing opposite data states into each of the ferroelectric capacitors in the memory circuit at the full power supply voltage level; (b) reducing the writing voltage by an incremental voltage; (c) writing opposite data states into each of the ferroelectric capacitors in the memory circuit at the reduced voltage; and (d) repeating steps (b) and (c) until the writing voltage has been reduced to a minimum voltage level.
Claim 31
Dependent Claim
175 words
A renewal method for imprinted ferroelectric capacitors in an integrated circuit memory comprising the steps of: fabricating a plurality of ferroelectric memory integrated circuits on a silicon wafer; thermally treating the wafer at a first temperature less than the Curie temperature of the ferroelectric material in the memory circuits; electrically testing the memory circuits at the wafer level to identify bad die that have failed the electrical test and good die that have passed the electrical test; electrically cycling the memory circuits; and electrically depoling the memory circuits to restore a virgin state in the ferroelectric capacitors, wherein the electrical depoling step comprises the steps of: (a) writing opposite data states into each of the ferroelectric capacitors in the memory circuit at the full power supply voltage level; (b) reducing the writing voltage by an incremental voltage; (c) writing opposite data states into each of the ferroelectric capacitors in the memory circuit at the reduced voltage; and (d) repeating steps (b) and (c) until the writing voltage has been reduced to a minimum voltage level.
Claim 32
Dependent Claim
171 words
A renewal method for avoiding imprinting of ferroelectric capacitors in an integrated circuit memory comprising the steps of: fabricating a plurality of ferroelectric memory integrated circuits on a silicon wafer; thermally treating the wafer at a first temperature less than the Curie temperature of the ferroelectric material in the memory circuits; electrically testing the memory circuits at the wafer level to identify bad die that have failed the electrical test and good die that have passed the electrical test; and electrically depoling the memory circuits to restore a virgin state in the ferroelectric capacitors, wherein the electrical depoling step comprises the steps of: (a) writing opposite data states into each of the ferroelectric capacitors in the memory circuit at the full power supply voltage level; (b) reducing the writing voltage by an incremental voltage; (c) writing opposite data states into each of the ferroelectric capacitors in the memory circuit at the reduced voltage; (d) repeating steps (b) and (c) until the writing voltage has been reduced to a minimum voltage level.
Claim 33
Dependent Claim
171 words
A renewal method for avoiding imprinting of ferroelectric capacitors in an integrated circuit memory comprising the steps of: fabricating a plurality of ferroelectric memory integrated circuits on a silicon wafer; thermally treating the wafer at a first temperature less than the Curie temperature of the ferroelectric material in the memory circuits; electrically testing the memory circuits at the wafer level to identify bad die that have failed the electrical test and good die that have passed the electrical test; and electrically depoling the memory circuits to restore a virgin state in the ferroelectric capacitors, wherein the electrical depoling step comprises the steps of: (a) writing opposite data states into each of the ferroelectric capacitors in the memory circuit at the full power supply voltage level; (b) reducing the writing voltage by an incremental voltage; (c) writing opposite data states into each of the ferroelectric capacitors in the memory circuit at the reduced voltage; (d) repeating steps (b) and (c) until the writing voltage has been reduced to a minimum voltage level.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-11 | 1999-12-11 | 2000-06-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-11 | 2003-12-11 | 2004-06-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-11 | 2007-12-11 | 2008-06-11 | $7700.00 | Window Closed / Lapsed |