US5523978A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Supply voltage detecting circuit of a semiconductor memory device
Assignee: Samsung Electronics Co Ltd
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Filing: 1994-07-05
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Granted: 1996-06-04
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Expires: 2014-07-05
Abstract
Abstract The present invention relates to a semiconductor memory device and more particularly to a power supply voltage detecting circuit of a semiconductor memory device which senses a voltage level of the power supply voltage. A power supply voltage detecting circuit of the present invention includes a circuit for generating a power supply voltage detecting signal by receiving a power supply voltage and a control circuit for generating a control signal in order to operate the circuit for generating the power supply voltage detecting signal when being in a specific mode state. The power supply voltage detecting circuit according to the present invention can reduce power consumption by cutting off a standby-current, since the power supply voltage detecting circuit is enabled during an activation of a chip. This allows the output signal of the power supply voltage detecting circuit to have an accurate voltage level of a power supply voltage or a ground voltage, so that chip operation speed can be improved and the effectiveness of the chip can be improved by removing noises.
Inventors
- 👤 Sei-Seung Yoon
- 👤 Jei-Hwan You
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 04:16
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C5/00; G11C5/14; G11C5/143; G11C5/147
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
51 words
A power-supply-voltage detecting circuit of a semiconductor memory device, comprising: means for generating a power-supply-voltage detecting signal by receiving a power supply voltage; and control means for generating a control signal to operate the means for generating the power-supply-voltage detecting signal when the semiconductor memory device is in an active state.
Claim 2
Dependent Claim
51 words
A power-supply-voltage detecting circuit of a semiconductor memory device, comprising: means for generating a power-supply-voltage detecting signal by receiving a power supply voltage; and control means for generating a control signal to operate the means for generating the power-supply-voltage detecting signal when the semiconductor memory device is in an active state.
Claim 3
Dependent Claim
100 words
A power-supply-voltage detecting circuit of a semiconductor memory device, comprising: reference-voltage generating means for generating a reference voltage of a constant voltage level by receiving a power supply voltage; comparison-voltage generating means for generating a comparison voltage by receiving the reference voltage; sense amplifying means for comparing the reference voltage and the comparison voltage and amplifying a voltage difference between the reference voltage and the comparison voltage to output a power-supply-voltage detecting signal; and control means for generating a control signal to operate the comparison-voltage generating means and the sense amplifying means when a chip is in an active state.
Claim 4
Dependent Claim
100 words
A power-supply-voltage detecting circuit of a semiconductor memory device, comprising: reference-voltage generating means for generating a reference voltage of a constant voltage level by receiving a power supply voltage; comparison-voltage generating means for generating a comparison voltage by receiving the reference voltage; sense amplifying means for comparing the reference voltage and the comparison voltage and amplifying a voltage difference between the reference voltage and the comparison voltage to output a power-supply-voltage detecting signal; and control means for generating a control signal to operate the comparison-voltage generating means and the sense amplifying means when a chip is in an active state.
Claim 5
Dependent Claim
23 words
The circuit as claimed in claim 2, wherein said control means generates said control signal in response to a row address strobe signal.
Claim 6
Dependent Claim
140 words
A power-supply-voltage detecting circuit of a semiconductor memory device, comprising: reference-voltage generating means for generating a reference voltage of a constant voltage level by receiving a power supply voltage; comparison-voltage generating means for generating a comparison voltage by receiving said reference voltage; sense amplifying means for outputting a power-supply-voltage detecting signal by receiving said reference voltage and said comparison voltage; latch means for latching the power-supply-voltage detecting signal by receiving said power-supply-voltage detecting signal and outputting the latched power-supply-voltage detecting signal; control means for generating a control signal in response to an input signal; and pulse generating means for generating a first pulse signal for operating the comparison-voltage generating means and the sense amplifying means in response to the control signal and generating a second pulse signal for controlling the latch means when a chip is in a specific mode.
Claim 7
Dependent Claim
140 words
A power-supply-voltage detecting circuit of a semiconductor memory device, comprising: reference-voltage generating means for generating a reference voltage of a constant voltage level by receiving a power supply voltage; comparison-voltage generating means for generating a comparison voltage by receiving said reference voltage; sense amplifying means for outputting a power-supply-voltage detecting signal by receiving said reference voltage and said comparison voltage; latch means for latching the power-supply-voltage detecting signal by receiving said power-supply-voltage detecting signal and outputting the latched power-supply-voltage detecting signal; control means for generating a control signal in response to an input signal; and pulse generating means for generating a first pulse signal for operating the comparison-voltage generating means and the sense amplifying means in response to the control signal and generating a second pulse signal for controlling the latch means when a chip is in a specific mode.
Claim 8
Dependent Claim
22 words
The circuit as claimed in claim 4, wherein said input signal inputted to said control means is a row address strobe signal.
Claim 9
Dependent Claim
47 words
The circuit as claimed in claim 4, wherein the first pulse signal and the second pulse signal are enabled in synchronism with the control signal and a second pulse width of the second pulse signal is shorter than a first pulse width of the first pulse signal.
References Cited (Backward Citations)
US4777626A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-04 | 1999-12-04 | 2000-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-04 | 2003-12-04 | 2004-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-04 | 2007-12-04 | 2008-06-04 | $7700.00 | Window Closed / Lapsed |