Sliding correlator for nanosecond pulses

Claim 2

A digital sliding correlator having means for producing a series of time-shifted stored copies of a digital character, means responsive to said shifted, stored copies of the character for selectively multiplying said shifted, stored copies by an input signal or a sign-inverted counterpart of the input signal responsive to the input signal, a first set of integrators and a second set of integrators, means for supplying to the first set of integrators first portions of said multiplied signals and for supplying to said second set of integrators second portions of said multiplied signals, and means for combining the outputs of said integrators.

Claim 3

A sliding correlation circuit comprising: a. a sign-inverting buffer amplifier connected to receive an input signal and provide a sign-inverted counterpart thereof; b. a multiplier shift register (MSR) connected to receive a copy of a character representation and providing a plurality of output digits constituting shifted, stored copies of said character representation; c. multiplier means connected to receive the input signal and the sign-inverted counterpart thereof, for providing as output, responsive to each output bit of the MSR a first one of the input signal and the sign-inverted counterpart thereof when the output digit is in a first state and the other one of the input signal and the sign-inverted counterpart thereof when the output digit is in a second state; d. first and second sets of integrators, each receiving an input and supplying an output; e. switching means for supplying to the first set of integrators a first set of outputs from the multiplier means and to the second set of integrators a second set of outputs from the multiplier means; and f. means for combining the outputs from the first and second sets of integrators.

Claim 4

A sliding correlation circuit comprising: a. a sign-inverting buffer amplifier connected to receive an input signal and provide a sign-inverted counterpart thereof; b. a multiplier shift register (MSR) connected to receive a copy of a character representation and providing a plurality of output digits constituting shifted, stored copies of said character representation; c. multiplier means connected to receive the input signal and the sign-inverted counterpart thereof, for providing as output, responsive to each output bit of the MSR a first one of the input signal and the sign-inverted counterpart thereof when the output digit is in a first state and the other one of the input signal and the sign-inverted counterpart thereof when the output digit is in a second state; d. first and second sets of integrators, each receiving an input and supplying an output; e. switching means for supplying to the first set of integrators a first set of outputs from the multiplier means and to the second set of integrators a second set of outputs from the multiplier means; and f. means for combining the outputs from the first and second sets of integrators.

Claim 5

The apparatus of claim 2 wherein the switching means comprises: (i) an alternating shift register means for producing a series of time-shifted stored copies of a digital character, and (ii) for each multiplier means output, a single-pole, double throw switch responsive to the state of a control signal to connect the multiplier means output to the selected one of the first and second sets of integrator means, the control signal being a selected output of the alternating shift register means.