Low noise low voltage phase lock loop

Claim 2

An amplifier stage for a ring-style, multi-stage VCO of a phase lock loop circuit, comprising: an input terminal for receiving a control voltage; a lowpass filter connected between the input terminal and a first reference voltage; a voltage to current converter stage including: a first MOS transistor M1 of a first type having a gate terminal connected to the input terminal, having a source terminal connected through a resistor R1 to the first reference voltage, and having a drain terminal; a diode-connected MOS transistor M2 of a second type having a drain terminal and a gate terminal connected together and to the drain terminal of the first MOS transistor M1, and having a source terminal connected to a second reference voltage; a current-source MOS transistor M8 of the second type having a source terminal connected to the second reference voltage, having a gate terminal connected to the drain of the first MOS transistor M1, and having a drain terminal wherein the transistor M8 mirrors current of transistor M1; a diode-connected transistor M9 of the first type having a gate terminal and a drain terminal connected together and to the drain terminal of transistor M8, and a source terminal connected to the first reference voltage; a differential amplifier stage including: a current-source MOS transistor M10 of the second type having a source terminal connected to the second reference voltage, having a gate terminal connected to the drain of the first MOS transistor M1, and having a drain terminal; a pair of MOS transistors M4 and M5 of the first type having source terminals connected together and to the drain terminal of the current-source MOS transistor M10, wherein a gate terminal of MOS transistor M4 is designated as an IN terminal, wherein a gate terminal of MOS transistor M5 is designated as an IN -- terminal, wherein a drain terminal of MOS transistor M4 provides an OUT -- signal for the differential amplifier stage, and wherein a drain terminal of MOS transistor M5 provides an OUT signal for the differential amplifier stage; a MOS transistor M6 of the first type, forming a load impedance for MOS transistor M4, wherein a drain terminal of MOS transistor M6 is connected to a drain terminal of MOS transistor M4, wherein a source terminal of MOS transistor M6 is connected to the first reference voltage, wherein a gate terminal of MOS transistor M6 is connected to the gate and drain terminals of the diode-connected transistor M9; a MOS transistor M7 of the first type, forming a load impedance for MOS transistor M5, wherein a drain terminal of MOS transistor M7 is connected to a drain terminal of MOS transistor M5, wherein a source terminal of MOS transistor M7 is connected to the first reference voltage, wherein a gate terminal of MOS transistor M7 is connected to the gate and drain terminals of the diode-connected transistor M9.

Claim 3

The amplifier stage of claim 1 wherein the first type of MOS transistor is an NMOS type and wherein the second type of MOS transistor is a PMOS type.

Claim 4

A phase lock loop circuit, comprising: a reference signal input terminal; a phase/frequency detector circuit, which has a first input terminal connected to the reference signal input terminal, which has a second input terminal, and which has an output terminal for providing a control voltage; a lowpass filter circuit connected to the output terminal of the phase/frequency detector circuit; a voltage-to-current converter stage which has an input terminal connected to the lowpass filter circuit, and which has an output terminal providing an output current proportional to the control voltage; said voltage-to-current converter including: a first MOS transistor M1 of a first type having a gate terminal connected to the lowpass filter circuit, having a source terminal connected through a resistor R1 to a first reference voltage, and having a drain terminal; a diode-connected MOS transistor M2 of a second type having a drain terminal and a gate terminal connected together and to the drain terminal of the first MOS transistor M1, and having a source terminal connected to a second reference voltage; a current-source MOS transistor M8 of the second type having a source terminal connected to the second reference voltage, having a gate terminal connected to the drain of the first MOS transistor M1, and having a drain terminal wherein the transistor M8 mirrors current of transistor M1; a diode-connected transistor M9 of the first type having a gate terminal and a drain terminal connected together and to the drain terminal of transistor M8, and a source terminal connected to the first reference voltage; two or more differential amplifier stages which are interconnected to form an oscillator circuit, each stage including: a current-source MOS transistor M10 of the second type having a source terminal connected to the second reference voltage, having a gate terminal connected to the drain of the first MOS transistor M1, and having a drain terminal; a pair of MOS transistors M4 and M5 of the first type having source terminals connected together and to the drain terminal of the current-source MOS transistor M10, wherein a gate terminal of MOS transistor M4 is designated as an IN terminal, wherein a gate terminal of MOS transistor M5 is designated as an IN -- terminal, wherein a drain terminal OUT -- of MOS transistor M4 provides an OUT -- signal for the differential amplifier stage, and wherein a drain terminal OUT of MOS transistor M5 provides an OUT signal for the differential amplifier stage; a MOS transistor M6 of the first type, forming a load impedance for MOS transistor M4, wherein a drain terminal of MOS transistor M6 is connected to a drain terminal of MOS transistor M4, wherein a source terminal of MOS transistor M6 is connected to the first reference voltage, wherein a gate terminal of MOS transistor M6 is connected to the gate and drain terminals of the diode-connected transistor M9; a MOS transistor M7 of the first type, forming a load impedance for MOS transistor M5, wherein a drain terminal of MOS transistor M7 is connected to a drain terminal of MOS transistor M5, wherein a source terminal of MOS transistor M7 is connected to the first reference voltage, wherein a gate terminal of MOS transistor M7 is connected to the gate and drain terminals of the diode-connected transistor M9; wherein the IN terminals and the IN -- terminals of each stage are connected to OUT and OUT -- terminals of another stage to provide a VCO for the phase lock loop circuit.

Claim 5

A phase lock loop circuit, comprising: a reference signal input terminal; a phase/frequency detector circuit, which has a first input terminal connected to the reference signal input terminal, which has a second input terminal, and which has an output terminal for providing a control voltage; a lowpass filter circuit connected to the output terminal of the phase/frequency detector circuit; a voltage-to-current converter stage which has an input terminal connected to the lowpass filter circuit, and which has an output terminal providing an output current proportional to the control voltage; said voltage-to-current converter including: a first MOS transistor M1 of a first type having a gate terminal connected to the lowpass filter circuit, having a source terminal connected through a resistor R1 to a first reference voltage, and having a drain terminal; a diode-connected MOS transistor M2 of a second type having a drain terminal and a gate terminal connected together and to the drain terminal of the first MOS transistor M1, and having a source terminal connected to a second reference voltage; a current-source MOS transistor M8 of the second type having a source terminal connected to the second reference voltage, having a gate terminal connected to the drain of the first MOS transistor M1, and having a drain terminal wherein the transistor M8 mirrors current of transistor M1; a diode-connected transistor M9 of the first type having a gate terminal and a drain terminal connected together and to the drain terminal of transistor M8, and a source terminal connected to the first reference voltage; two or more differential amplifier stages which are interconnected to form an oscillator circuit, each stage including: a current-source MOS transistor M10 of the second type having a source terminal connected to the second reference voltage, having a gate terminal connected to the drain of the first MOS transistor M1, and having a drain terminal; a pair of MOS transistors M4 and M5 of the first type having source terminals connected together and to the drain terminal of the current-source MOS transistor M10, wherein a gate terminal of MOS transistor M4 is designated as an IN terminal, wherein a gate terminal of MOS transistor M5 is designated as an IN -- terminal, wherein a drain terminal OUT -- of MOS transistor M4 provides an OUT -- signal for the differential amplifier stage, and wherein a drain terminal OUT of MOS transistor M5 provides an OUT signal for the differential amplifier stage; a MOS transistor M6 of the first type, forming a load impedance for MOS transistor M4, wherein a drain terminal of MOS transistor M6 is connected to a drain terminal of MOS transistor M4, wherein a source terminal of MOS transistor M6 is connected to the first reference voltage, wherein a gate terminal of MOS transistor M6 is connected to the gate and drain terminals of the diode-connected transistor M9; a MOS transistor M7 of the first type, forming a load impedance for MOS transistor M5, wherein a drain terminal of MOS transistor M7 is connected to a drain terminal of MOS transistor M5, wherein a source terminal of MOS transistor M7 is connected to the first reference voltage, wherein a gate terminal of MOS transistor M7 is connected to the gate and drain terminals of the diode-connected transistor M9; wherein the IN terminals and the IN -- terminals of each stage are connected to OUT and OUT -- terminals of another stage to provide a VCO for the phase lock loop circuit.

Claim 6

The phase lock loop circuit of claim 3 wherein the first type of MOS transistor is an NMOS type and wherein the second type of MOS transistor is a PMOS type.