US5519237A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Renesas Electronics Corp
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Filing: 1994-06-22
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Granted: 1996-05-21
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Expires: 2014-06-22
Abstract
Abstract A first interlayer insulating film having a second contact hole is formed on a main surface of a semiconductor substrate 1 in a peripheral circuitry. A second plug electrode of the same material as a first plug electrode in a memory cell array is formed in the second contact hole. A pad layer is formed over the second plug electrode and a top surface of the first interlayer insulating film. The pad layer and a capacitor lower electrode are made of the same material. The pad layer is covered with the second interlayer insulating film. A third contact hole is formed at a portion of the second interlayer insulating film located above the pad layer. A first aluminum interconnection layer is formed in the third contact hole. Thereby, a contact can be formed easily between the interconnection layer and the main surface of the semiconductor substrate in the peripheral circuitry of a DRAM, and a manufacturing process can be simplified.
Inventors
- 👤 Hiromi Itoh
- 👤 Tomonori Okudaira
- 👤 Keiichiro Kashihara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 16:09
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/01; H10B12/09; H10B12/02; H10B12/03
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
209 words
A semiconductor memory device including a memory cell portion and a peripheral circuit portion on a main surface of a semiconductor substrate, said memory cell portion including memory cells for storing information and said peripheral circuit portion including peripheral circuits for controlling an operation of said memory cells, said semiconductor memory device, comprising; a first interlayer insulating film which is provided with a first opening at a predetermined position in said memory cell portion of said semiconductor substrate and a second opening at a predetermined position in said peripheral circuit portion of said semiconductor substrate; first and second plug electrodes formed in said first and second openings, respectively; a capacitor lower electrode formed on and electrically connected to said first plug electrode; a capacitor dielectric film covering said capacitor lower electrode; a capacitor upper electrode covering said capacitor dielectric film; a pad layer formed on a top surface of said second plug electrode and a top surface of said first interlayer insulating film and electrically connected to said second plug electrode; a second interlayer insulating film formed on said pad layer and having a third opening located above said pad layer; and an interconnection layer formed at least in said third opening and electrically connected to said pad layer.
Claim 2
Dependent Claim
209 words
A semiconductor memory device including a memory cell portion and a peripheral circuit portion on a main surface of a semiconductor substrate, said memory cell portion including memory cells for storing information and said peripheral circuit portion including peripheral circuits for controlling an operation of said memory cells, said semiconductor memory device, comprising; a first interlayer insulating film which is provided with a first opening at a predetermined position in said memory cell portion of said semiconductor substrate and a second opening at a predetermined position in said peripheral circuit portion of said semiconductor substrate; first and second plug electrodes formed in said first and second openings, respectively; a capacitor lower electrode formed on and electrically connected to said first plug electrode; a capacitor dielectric film covering said capacitor lower electrode; a capacitor upper electrode covering said capacitor dielectric film; a pad layer formed on a top surface of said second plug electrode and a top surface of said first interlayer insulating film and electrically connected to said second plug electrode; a second interlayer insulating film formed on said pad layer and having a third opening located above said pad layer; and an interconnection layer formed at least in said third opening and electrically connected to said pad layer.
Claim 3
Dependent Claim
23 words
A semiconductor memory device according to claim 1, wherein said pad layer and said capacitor lower electrode are made of the same material.
Claim 4
Dependent Claim
37 words
A semiconductor memory device according to claim 1, wherein said capacitor lower electrode and said first plug electrode are integral with each other, and said pad layer and said second plug electrode are integral with each other.
Claim 5
Dependent Claim
27 words
A semiconductor memory device according to claim 1, wherein said pad layer and said capacitor lower electrode are made of noble metal having a high melting point.
Claim 6
Dependent Claim
33 words
A semiconductor memory device according to claim 4, wherein said capacitor lower electrode and said pad layer are made of at least one material selected from the group consisting of Pt and Pd.
Claim 7
Dependent Claim
22 words
A semiconductor memory device according to claim 1, wherein said capacitor dielectric film is made of material having a high dielectric constant.
Claim 8
Dependent Claim
58 words
A semiconductor memory device according to claim 1, wherein said pad layer further comprises a first layer formed on a top surface of said second plug electrode and a second layer formed on top of said first layer, wherein said first layer is formed of a material which is nonreactive with a material of said second plug electrode.
Claim 9
Dependent Claim
69 words
A semiconductor memory device according to claim 1, wherein said capacitor lower electrode further comprises a first layer formed on top surface of said first plug electrode and a second layer formed on top of said first layer, wherein said first layer is formed of a material which is non-reactive with a material of said first plug electrode and said second layer forms a substrate for said dielectric material.
Claim 10
Dependent Claim
44 words
A semiconductor memory device according to claim 1, wherein each of said first and second plug electrodes comprise polysilicon selectively ion-implanted with an impurity type corresponding to that portion of the semiconductor substrate underlying a corresponding one of said first and second plug electrodes.
Claim 11
Dependent Claim
29 words
A semiconductor memory device according to claim 1, wherein said third opening is formed on said pad layer positioned on said top surface of said first interlayer insulating film.
References Cited (Backward Citations)
US5323343A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-05-21 | 1999-11-20 | 2000-05-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-05-21 | 2003-11-20 | 2004-05-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-05-21 | 2007-11-20 | 2008-05-21 | $7700.00 | Window Closed / Lapsed |