US5517438A
Expired / Lapsed
US
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Fast multiply-add instruction sequence in a pipeline floating-point processor
Assignee: International Business Machines Corp
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Filing: 1994-07-20
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Granted: 1996-05-14
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Expires: 2014-07-20
Abstract
Abstract A pipeline floating point processor in which the addition pipelining is reorganized so that no wait cycle is needed when the addition uses the result of an immediately foregoing multiplication (fast multiply-add instruction). The reorganization implies the following changes of an existing data flow of the pipeline floating processor: data feed-back via path ND of normalized data from the multiplier M into the aligners AL1 and AL2; shift left one digit feature on both sides of the data path for taking account of a possible leading zero digit of the product, and special zeroing of potential guard digits by Z1 and Z2; exponent build by 9 bits for overflow and underflow recognition, and due to an underflow the exponent result, is reset to zero on the fly by a true zero unit (T/C).
Inventors
- 👤 Son Dao-Trong
- 👤 Juergen Haas
- 👤 Rolf Mueller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 17:05
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/544; G06F7/5443; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/386; G06F2207/3884; G06F7/483
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
294 words
A floating point processor comprising: a multiply section having: a first input register and a second input register for intermediately storing first and second operands, a multiplier coupled to the first and second input registers for performing a multiplication of the first and second operands, adder output registers coupled to the multiplier for intermediately storing partial sums of the multiplication, a first adder coupled to the adder output registers for performing an addition of the partial sums, and a first normalizer connected to the first adder for normalizing a result of the addition of the partial sums; and an add section having: a third input register and a fourth input register for intermediately storing the first and second operands, a first aligner connected to said third input register for aligning the first operand, a first left shifter connected to the first aligner, a second aligner connected to said fourth input register for aligning the second operand, a second left shifter connected to the second aligner, a true/complement unit coupled to the first left shifter for operand true/complement building, a first zero setter connected to the true/complement unit, a first adder input register coupled to the first zero setter for intermediately storing an output of the first zero setter, a second zero setter connected to the second left shifter, a second adder input register coupled to the second zero setter for intermediately storing an output of the second zero setter, a second adder coupled to the first and second adder input registers for adding outputs of the first and second adder input registers, a second normalizer connected to said second adder for normalizing an output of said second adder; and a feedback path connecting said first normalizer to each of said first and second aligners.
Claim 2
Dependent Claim
294 words
A floating point processor comprising: a multiply section having: a first input register and a second input register for intermediately storing first and second operands, a multiplier coupled to the first and second input registers for performing a multiplication of the first and second operands, adder output registers coupled to the multiplier for intermediately storing partial sums of the multiplication, a first adder coupled to the adder output registers for performing an addition of the partial sums, and a first normalizer connected to the first adder for normalizing a result of the addition of the partial sums; and an add section having: a third input register and a fourth input register for intermediately storing the first and second operands, a first aligner connected to said third input register for aligning the first operand, a first left shifter connected to the first aligner, a second aligner connected to said fourth input register for aligning the second operand, a second left shifter connected to the second aligner, a true/complement unit coupled to the first left shifter for operand true/complement building, a first zero setter connected to the true/complement unit, a first adder input register coupled to the first zero setter for intermediately storing an output of the first zero setter, a second zero setter connected to the second left shifter, a second adder input register coupled to the second zero setter for intermediately storing an output of the second zero setter, a second adder coupled to the first and second adder input registers for adding outputs of the first and second adder input registers, a second normalizer connected to said second adder for normalizing an output of said second adder; and a feedback path connecting said first normalizer to each of said first and second aligners.
Claim 3
Dependent Claim
247 words
(Amended) A method of performing a fast multiply-add instruction without requiring a wait cycle in a floating point processor comprising the steps of: (a) reading first and second operands for multiplication into first and second input registers of a multiplier; (b) building partial sums of the first and second operands by the multiplier; (c) calculating a product exponent and reducing the exponent by 1 if a product has a leading zero, including simultaneously reading an operand (addend) of an addition; (d) adding the partial sums from the multiplier including feeding a resulting intermediate value (product) back to aligners via a feed-back path; (e) comparing exponents of said product and, if they do not compare, performing a proper alignment; (f) testing whether the following cases apply: i) if the product is true zero then said feeding back to aligners of step (d) is cancelled; ii) if the product exponent is smaller than or equal to the addend exponent, then the product is aligned; iii) if the product exponent is greater than the addend exponent, then the addend is aligned; (g) setting a potential guard digit of the product to zero if the product does not have a leading zero; (h) if the product has a leading zero, shifting both operands left by 1 digit and a least significant digit of an aligner becomes a guard digit of a result; (i) aligning both the product and the addend including adding them in the second Adder forming a final result.
Claim 4
Dependent Claim
247 words
(Amended) A method of performing a fast multiply-add instruction without requiring a wait cycle in a floating point processor comprising the steps of: (a) reading first and second operands for multiplication into first and second input registers of a multiplier; (b) building partial sums of the first and second operands by the multiplier; (c) calculating a product exponent and reducing the exponent by 1 if a product has a leading zero, including simultaneously reading an operand (addend) of an addition; (d) adding the partial sums from the multiplier including feeding a resulting intermediate value (product) back to aligners via a feed-back path; (e) comparing exponents of said product and, if they do not compare, performing a proper alignment; (f) testing whether the following cases apply: i) if the product is true zero then said feeding back to aligners of step (d) is cancelled; ii) if the product exponent is smaller than or equal to the addend exponent, then the product is aligned; iii) if the product exponent is greater than the addend exponent, then the addend is aligned; (g) setting a potential guard digit of the product to zero if the product does not have a leading zero; (h) if the product has a leading zero, shifting both operands left by 1 digit and a least significant digit of an aligner becomes a guard digit of a result; (i) aligning both the product and the addend including adding them in the second Adder forming a final result.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-05-14 | 1999-11-13 | 2000-05-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-05-14 | 2003-11-13 | 2004-05-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-05-14 | 2007-11-13 | 2008-05-14 | $7700.00 | Window Closed / Lapsed |