Method and apparatus for operating polyphase DC motors using a PWM chopping signal in zero crossing determination

Claim 2

A circuit for operating a polyphase dc motor having a plurality of driving coils, comprising: a plurality of drive transistors, each coupled to an associated one of the plurality of driving coils, for providing instantaneous drive currents thereto; a sequencer for generating control signals to said plurality of drive transistors in such a manner that drive current is provided to a driving coil selected according to each of a plurality of phases in a predetermined commutation sequence; circuitry for detecting zero crossings of a back emf voltage of a coil that is connected into a floating state during each of said phases to produce a back emf detection signal for timing changes among said phases; PWM circuitry for gating the control signals applied to said plurality of drive transistors in such a manner that drive current is provided to the selected driving coil a plurality of times within each phase; and circuitry, having an input coupled to said PWM circuitry and having an output coupled to said detecting circuitry, for disabling zero crossing detection for a selected delay time relative to the gating of the control signals, and for thereafter enabling zero crossing detection, each of such disabling and enabling operations occurring a plurality of times within each phase.

Claim 3

The circuit of claim 1 wherein said gating circuitry comprises: circuitry for sensing the drive current in the driving coils; and circuitry for generating a chop signal when the sensed current exceeds a threshold.

Claim 4

The circuit of claim 2 wherein said disabling and enabling circuitry comprises circuitry for controlling a back emf sampling time to allow sampling at time of minimum back emf induced noise.

Claim 5

The circuit of claim 3 wherein said disabling and enabling circuitry comprises circuitry for controlling a back emf sampling time to allow sampling only between times when the plurality of drive transistors applies drive currents to selected ones of said driving coils.

Claim 6

The circuit of claim 3 wherein said disabling and enabling circuitry further comprises a flip-flop that is clocked by the PWM circuitry.

Claim 7

The circuit of claim 5 wherein said flip-flop is connected to receive an output of said detecting circuitry.

Claim 8

The circuit of claim 1 wherein polyphase dc motor is a sensorless, brushless polyphase dc motor.

Claim 9

A circuit for operating a sensorless polyphase dc motor having a plurality of driving coils in a non-PWM operating mode and in a PWM mode, comprising: a commutation sequencer for producing signals according to a commutation sequence having a plurality of phases to identify which of said driving coils are to be active to receive instantaneous drive currents and which are to be connected into a floating state; drive circuitry for connecting said coils to receive the instantaneous drive currents and into the floating state in accordance with the signals from said commutation sequencer; circuitry for detecting zero crossings of a back emf voltage of the one of the plurality of driving coils that is connected into the floating state in each phase to produce a back emf detection signal; circuitry responsive to the back emf detection signal for producing a delayed signal to increment the commutation sequencer to a next phase in the commutation sequence; circuitry for generating a chop signal when the current in said active coils exceeds a predetermined threshold; circuitry, operable in the PWM mode, for turning the drive currents supplied to the selected active coils on and off to modulate the drive currents in accordance with said chop signal; and circuitry, operable in the PWM mode, for delaying detection of zero crossings according to said chop signal, said delaying circuitry being disabled from delaying such detection in the non-PWM operating mode.

Claim 10

A circuit for operating a sensorless polyphase dc motor having a plurality of driving coils in a non-PWM operating mode and in a PWM mode, comprising: a commutation sequencer for producing signals according to a commutation sequence having a plurality of phases to identify which of said driving coils are to be active to receive instantaneous drive currents and which are to be connected into a floating state; drive circuitry for connecting said coils to receive the instantaneous drive currents and into the floating state in accordance with the signals from said commutation sequencer; circuitry for detecting zero crossings of a back emf voltage of the one of the plurality of driving coils that is connected into the floating state in each phase to produce a back emf detection signal; circuitry responsive to the back emf detection signal for producing a delayed signal to increment the commutation sequencer to a next phase in the commutation sequence; circuitry for generating a chop signal when the current in said active coils exceeds a predetermined threshold; circuitry, operable in the PWM mode, for turning the drive currents supplied to the selected active coils on and off to modulate the drive currents in accordance with said chop signal; and circuitry, operable in the PWM mode, for delaying detection of zero crossings according to said chop signal, said delaying circuitry being disabled from delaying such detection in the non-PWM operating mode.

Claim 11

The circuit of claim 8 wherein said drive circuitry is a triple--1/2--H--bridge, and comprises FET power transistors.

Claim 12

The circuit of claim 8 wherein said circuitry for detecting zero crossings of a back emf voltage comprises a comparator switchably connected to each coil when it is connected in a floating state operable to produce an output when the voltage on the floating coil crosses a reference voltage,

Claim 13

The circuit of claim 9 wherein said circuitry for turning the drive currents supplied to the selected active coils on and off comprises circuitry for generating a chop signal when the current in said active coils exceeds a predetermined threshold.

Claim 14

The circuit of claim 8 wherein said circuitry for delaying a detection of a next zero crossing comprises circuitry for controlling a back emf sampling time to allow sampling at time when minimum back emf induced noise exists on the floating coil,

Claim 15

The circuit of claim 12 wherein said circuitry for delaying detection of zero crossings comprises circuitry for controlling a back emf sampling time to allow sampling only between times when the circuitry for turning the drive currents supplied to the selected active coils on and off controls the drive current to be turned on and when the drive circuitry actually connects said coils to receive the instantaneous drive currents.

Claim 16

The circuit of claim 13 wherein said circuitry for delaying detection of zero crossings further comprises a flip-flop that is clocked by the circuitry for controlling the drive currents to said selected driving coils to be turned on and off.

Claim 17

The circuit of claim 14 wherein said flip-flop is connected to receive an output of said circuitry for detecting zero crossings.

Claim 18

The circuit of claim 8 wherein the polyphase dc motor is a sensorless, brushless polyphase dc motor.

Claim 21

The method of claim 17 wherein said chopping is performed as a part of a PWM operation.

Claim 22

The circuit of claim 18 wherein said inhibiting is performed for a time sufficient to allow PWM induced noise to be minimum.

Claim 23

The circuit of claim 18 wherein said inhibiting is performed to allow sampling only between times when the drive current circuitry controls the drive current to be turned on and when the circuit to provide instantaneous drive currents to selected ones of said driving coils actually applies current.