US5515522A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Coherence index generation for use by an input/output adapter located outside of the processor to detect whether the updated version of data resides within the cache
Assignee: Hewlett Packard Development Co LP
•
Filing: 1994-02-24
•
Granted: 1996-05-07
•
Expires: 2014-02-24
Abstract
Abstract A computing system includes a memory bus, a main memory, an I/O adapter and a processor. The main memory, the I/O adapter and the processor are connected to the bus. The I/O adapter includes a translation map. The translation map maps I/O page numbers to memory address page numbers. The translation map includes coherence indices. The processor includes a cache and an instruction execution means. The instruction execution means generates coherence indices to be stored in the translation map. The instruction execution means performs in hardware a hash operation to generate the coherence indices.
Inventors
- 👤 K. Monroe Bridges
- 👤 William R. Bryg
- 👤 Stephen G. Burger
- 👤 James M. Hull
- 👤 Michael L. Ziegler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 11:12
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F12/0835
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
192 words
A computing system, comprising: an intercomect means for providing information transfer; a main memory coupled to the interconnect means; an I/O adapter, coupled to the interconnect means, the I/O adapter including a translation map, the translation map mapping I/O page numbers to memory address page numbers, the trmslation map including coherence indices; and, a processor, coupled to the interconnect means, the processor including a cache and instruction execution means for, in response to an instruction executed by the processor, generating a coherence index to be stored in the translation map, the instruction execution memos performing in hardware a hash operation to generate the coherence index, wherein the I/O adapter is not contained within the processor; wherein when the I/O adapter forwards the coherence index from the I/O adapter to the processor during performance of a data transfer, the processor uses the coherence index to detect whether an updated version of relevant data resides within the cache, and when the processor detects that an updated version of relevant data resides within the cache, the updated version of relevant data is used for the data transfer rather than stale data within the main memory.
Claim 2
Dependent Claim
192 words
A computing system, comprising: an intercomect means for providing information transfer; a main memory coupled to the interconnect means; an I/O adapter, coupled to the interconnect means, the I/O adapter including a translation map, the translation map mapping I/O page numbers to memory address page numbers, the trmslation map including coherence indices; and, a processor, coupled to the interconnect means, the processor including a cache and instruction execution means for, in response to an instruction executed by the processor, generating a coherence index to be stored in the translation map, the instruction execution memos performing in hardware a hash operation to generate the coherence index, wherein the I/O adapter is not contained within the processor; wherein when the I/O adapter forwards the coherence index from the I/O adapter to the processor during performance of a data transfer, the processor uses the coherence index to detect whether an updated version of relevant data resides within the cache, and when the processor detects that an updated version of relevant data resides within the cache, the updated version of relevant data is used for the data transfer rather than stale data within the main memory.
Claim 3
Dependent Claim
63 words
A computing system as in claim 1 wherein the instruction specifies a load coherence index operation, a virtual memory offset and a space identification, and wherein the instruction execution means, in response to the intruction performs the hash operation on a subset of bits from the virtual memory offset and a subset of bits from the space identification to generate the coherence index.
Claim 4
Dependent Claim
40 words
A computing system as in claim 2 wherein the virtual memory offset is stored in a first general register, the space identification is stored in a second general register and the coherence index is placed in a target general register.
Claim 5
Dependent Claim
37 words
A computing system as in claim 3 wherein the instruction specifies the virtual memory offset by identifying the first general register, specifies the space identification by identifying the second general register and specifies the target general register.
Claim 6
Dependent Claim
96 words
A computing system as in claim 1 wherein the instruction specifies a base register, an index register, a space register select and a target register, and wherein the instruction execution means, in response to the instruction, generates a space identification from information stored in the base register and the space register select, generates an offset from information stored in the base register and information stored in the index register, and performs the hash operation on a subset of bits from the offset and a subset of bits from the space identification to generate the coherence index.
Claim 7
Dependent Claim
50 words
A computing system as in claim 5 wherein the base register is a first general register which currently stores a base value, the index register is a second general register which currently stores an index value, the target register is a third general register which will receive the coherence index.
Claim 8
Dependent Claim
23 words
A computing system as in claim 1 wherein the instruction specifies at least one register that is used to generate a virtual address.
Claim 9
Dependent Claim
167 words
In a computing system, a method comprising the steps of: (a) generating a coherence index by a processor comprising the substep of (a.1) in response to a load coherence index instruction executed by the processor, performing in hardware a hash operation to generate the coherence index; (b) storing the coherence index in a translation map within an I/O adapter, the I/O adapter not being contained within the processor; (c) forwarding the coherence index from the I/O adapter to the processor upon performing a data transfer; and, (d) upon the processor receiving the coherence index from the I/O adapter in step (c), using the coherence index by the processor to detect whether an updated version of relevant data resides within a cache within the processor, and when the processor detects that an up dated version of relevant data resides within the cache, the updated version of relevant data is used for the data transfer rather than stale data within a main memory which is external to the processor.
Claim 10
Dependent Claim
167 words
In a computing system, a method comprising the steps of: (a) generating a coherence index by a processor comprising the substep of (a.1) in response to a load coherence index instruction executed by the processor, performing in hardware a hash operation to generate the coherence index; (b) storing the coherence index in a translation map within an I/O adapter, the I/O adapter not being contained within the processor; (c) forwarding the coherence index from the I/O adapter to the processor upon performing a data transfer; and, (d) upon the processor receiving the coherence index from the I/O adapter in step (c), using the coherence index by the processor to detect whether an updated version of relevant data resides within a cache within the processor, and when the processor detects that an up dated version of relevant data resides within the cache, the updated version of relevant data is used for the data transfer rather than stale data within a main memory which is external to the processor.
Claim 11
Dependent Claim
62 words
A method as in claim 8 wherein in substep (a.1) the load coherence index instruction specifies a load coherence index operation, a virtual memory offset and a space identification, and wherein substep (a.1) includes performing a hash operation on a subset of bits from the virtual memory offset and a subset of bits from the space identification to generate the coherence index.
Claim 12
Dependent Claim
42 words
A method as in claim 9 wherein in substep (a.1) the virtual memory offset is stored in a first general register, the space identification is stored in a second general register and the coherence index is placed in a target general register.
Claim 13
Dependent Claim
42 words
A method as in claim 10 wherein in substep (a.1) the load coherence index instruction specifies the virtual memory offset by identifying the first general register, specifies the space identification by identifying the second general register and specifies the target general register.
Claim 14
Dependent Claim
95 words
A method as in claim 8 wherein in substep (a.1), the load coherence index instruction specifies a base register, an index register, a space register select and a target register, and wherein substep (a.1) includes generating a space identification from information stored in the base register and the space register select, generating an offset from information stored in the base register and information stored in the index register and performing a hash operation on a subset of bits from the offset and a subset of bits from the space identification to generate the coherence index.
Claim 15
Dependent Claim
52 words
A method as in claim 12 wherein in substep (a.1) the base register is a first general register which currently stores a base value, the index register is a second general register which currently stores an index value, the target register is a third general register which will receive the coherence index.
Claim 16
Dependent Claim
34 words
A method as in claim 8 wherein in substep (a.1) the load coherence index instruction specifies a load coherence index operation and at least one register which is used to generate a virtual address.
Claim 17
Dependent Claim
147 words
A processor comprising: a cache; and, instruction execution means, coupled to the cache, for, in response to an instruction executed by the processor, generating a coherence index to be stored in a translation map within a I/O adapter, the instruction execution means performing in hardware a hash operation to generate the coherence index; wherein the I/O adapter is not contained within the processor, and wherein when the I/O adapter forwards the coherence index from the I/O adapter to the processor during performance of a data transfer, the processor uses the coherence index to detect whether an updated version of relevant data resides within the cache, and when the processor detects that an updated version of relevant data resides within the cache, the updated version of relevant data is used for the data transfer rather than stale data within a main memory which is external to the processor.
Claim 18
Dependent Claim
147 words
A processor comprising: a cache; and, instruction execution means, coupled to the cache, for, in response to an instruction executed by the processor, generating a coherence index to be stored in a translation map within a I/O adapter, the instruction execution means performing in hardware a hash operation to generate the coherence index; wherein the I/O adapter is not contained within the processor, and wherein when the I/O adapter forwards the coherence index from the I/O adapter to the processor during performance of a data transfer, the processor uses the coherence index to detect whether an updated version of relevant data resides within the cache, and when the processor detects that an updated version of relevant data resides within the cache, the updated version of relevant data is used for the data transfer rather than stale data within a main memory which is external to the processor.
Claim 19
Dependent Claim
62 words
A processor as in claim 15 wherein the instruction specifies a load coherence index operation, a virtual memory offset and a space identification, and wherein the instruction execution means, in response to the instruction, performs the hash operation on a subset of bits from the virtual memory offset and a subset of bits from the space identification to generate the coherence index.
Claim 20
Dependent Claim
39 words
A processor as in claim 16 wherein the virtual memory offset is stored in a first general register, the space identification is stored in a second general register and the coherence index is placed in a target general register.
Claim 21
Dependent Claim
36 words
A processor as in claim 17 wherein the instruction specifies the virtual memory offset by identifying the first general register, specifies the space identification by identifying the second general register and specifies the target general register.
Claim 22
Dependent Claim
94 words
A processor as in claim 15 wherein the instruction specifies a base register, an index register, a space register select and a target register, and wherein the instruction execution means, in response to the instruction, generates a space identification from information stored in the base register and the space register select, generates an offset from information stored in the base register and information stored in the index register, and performs hash operation on a subset of bits from the offset and a subset of bits from the space identification to generate the coherence index.
Claim 23
Dependent Claim
49 words
A processor as in claim 19 wherein the base register is a first general register which currently stores a base value, the index register is a second general register which currently stores an index value, the target register is a third general register which will receive the coherence index.
Claim 24
Dependent Claim
23 words
A computing system as in claim 15 wherein the instruction specifies at least one register that is used to generate a virtual address.
References Cited (Backward Citations)
EP0140522A2
Cited
US4680700A
Cited
EP0212129A2
Cited
US4885680A
Cited
US4797817A
Cited
US5438670A
Cited
US5029070A
Cited
US5025365A
Cited
US5197133A
Cited
US5155843A
Cited
US5404467A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-05-07 | 1999-11-06 | 2000-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-05-07 | 2003-11-06 | 2004-05-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-05-07 | 2007-11-06 | 2008-05-07 | $7700.00 | Window Closed / Lapsed |