Data processing system having a switching network connecting multiple peripheral devices using data paths capable of different data bus widths

Claim 2

A data processing apparatus comprising: a first (k×m)-bit data bus for transmitting data of (k×m)-bits in parallel wherein k and m are an integer larger than one; at least one (k×m)-bit I/O peripheral device connected to said first (k×m)-bit data bus; a first m-bit data bus group consisting of first to k-th m-bit data buses obtained by dividing said first (k×m)-bit data bus into k data buses having an equal width of data bus; a plurality of m-bit I/O peripheral devices each of which is connected to one m-bit data bus belonging to said first m-bit data bus group; a second (k×m)-bit data bus; a (k×m)-bit I/O central processing unit connected to said second (k×m)-bit data bus; a second m-bit data bus group consisting of (k+1)-th to k-th m-bit data buses obtained by dividing said second (k×m)-bit data bus into k data buses having an equal width of data bus; a transmission control means for generating control signals responsive to a demand of data transmission from said CPU; and a data path switching means connected between said first m-bit data bus group and second m-bit data bus group which forms a data transmission path between an arbitrary two of said plurality of m-bit I/O peripheral devices, said at least one (k×m)-bit I/O peripheral device and said CPU in response to a control signal output from said transmission control means.

Claim 3

A data processing apparatus comprising: a first (k×m)-bit data bus for transmitting data of (k×m)-bits in parallel wherein k and m are an integer larger than one at least one (k×m)-bit I/O peripheral device connected to said first (k×m)-bit data bus; a first m-bit data bus group consisting of first to k-th m-bit data buses obtained by dividing said first (k×m)-bit data bus into k data buses having an equal width of data bus; a plurality of m-bit I/O data bus belonging to said first m-bit data bus group; a second (k×m)-bit data bus; a (k×m)-bit I/O central processing unit connected to said second (k×m)-bit data bus; a data path switching means connected between said first and second m-bit data bus groups which comprises a first group of m-bit bus transceivers each connecting one m-bit data bus belonging to said first group and a corresponding m-bit data bus belonging to said second group and a second group m-bit bus transceivers each connecting two m-bit data buses belonging to said second group; and a transmission control means for generating control signals responsive to a data transmission demand from said CPU and for selectively controlling said m-bit bus transceivers belonging to said first and second transceiver groups and said m-bit I/O peripheral devices corresponding to the control signals, thereby forming at least one data transmission path between two arbitrary devices selected from among said m-bit I/O peripheral devices, at least one (k×m)-bit I/O peripheral device and said CPU.

Claim 4

A data processing apparatus comprising: a first (k×m)-bit data bus for transmitting data of (k×m)-bits in parallel wherein k and m are an integer larger than one at least one (k×m)-bit I/O peripheral device connected to said first (k×m)-bit data bus; a first m-bit data bus group consisting of first to k-th m-bit data buses obtained by dividing said first (k×m)-bit data bus into k data buses having an equal width of data bus; a plurality of m-bit I/O data bus belonging to said first m-bit data bus group; a second (k×m)-bit data bus; a (k×m)-bit I/O central processing unit connected to said second (k×m)-bit data bus; a data path switching means connected between said first and second m-bit data bus groups which comprises a first group of m-bit bus transceivers each connecting one m-bit data bus belonging to said first group and a corresponding m-bit data bus belonging to said second group and a second group m-bit bus transceivers each connecting two m-bit data buses belonging to said second group; and a transmission control means for generating control signals responsive to a data transmission demand from said CPU and for selectively controlling said m-bit bus transceivers belonging to said first and second transceiver groups and said m-bit I/O peripheral devices corresponding to the control signals, thereby forming at least one data transmission path between two arbitrary devices selected from among said m-bit I/O peripheral devices, at least one (k×m)-bit I/O peripheral device and said CPU.

Claim 5

The data processing apparatus as claimed in claim 1 wherein said data path switching means forms a (k×m)-bit data path between said first and second (k×m) bit data buses in response to a demand requesting data transmission therebetween.

Claim 6

The data processing apparatus as claimed in claim 1 wherein said plurality of m-bit peripheral devices include at least one m-bit register.

Claim 7

The data processing apparatus as claimed in claim 1 wherein said data path switching means comprises a first group consisted of a plurality of m-bit bus transceivers each connecting between two of said m-bit data buses consisting said first group, and a second group of m-bit bus transceivers each connecting one of said m-bit data buses consisting said first group and one of said m-bit data buses consisting said second group at an m-bit position corresponding to each other.

Claim 8

The data processing apparatus as claimed in claim 5 wherein m-bit registers are connected to respective m-bit data buses of said first group.

Claim 9

The data processing apparatus as claimed in claim 1 wherein said data path switching means comprises a (2k+1)-th m-bit data bus which is connected to said m-bit data buses of said first group via m-bit bus transceivers consisting a first group of transceivers, and m-bit bus transceivers consisting a second group of transceivers each of which connects one of said m-bit data buses of said first group with corresponding one of said m-bit data buses of said second group.

Claim 10

The data processing apparatus as claimed in claim 7, further comprises m-bit registers each connected to one of said m-bit data buses of said first group.

Claim 11

The data processing apparatus as claimed in claim 2, wherein said data path switching means forms an m-bit data path between two arbitrary devices selected from among said m-bit peripheral devices by enabling one m-bit bus transceiver belonging to said first transceiver group in response to a demand requesting data transmission therebetween.

Claim 12

The data processing apparatus as claimed in claim 2, wherein said data path switching means forms an m-bit data path between one of said plurality of m-bit data buses belonging to said first group and one of said plurality of m-bit data buses belonging to said second group by enabling one m-bit bus transceiver belonging to said second transceiver group in response to a demand requesting data transmission therebetween.

Claim 13

The data processing apparatus as claimed in claim 2, wherein said data path switching means forms a (k×m)-bit data path between said first and second (k×m) bit data bus groups by enabling all m-bit bus transceivers belonging to said second transceiver group in response to a demand requesting data transmission therebetween.

Claim 14

The data processing apparatus as claimed in claim 2, wherein said plurality of m-bit peripheral devices include at least one m-bit register.

Claim 15

The data processing apparatus as claimed in claim 2, further comprising one m-bit data bus disposed between said first transceiver group and second transceiver group in such a manner that any transceiver belonging to said first group is able to communicate with any transceiver belonging to said second group.