High Speed ATM switch with simplified arbitration scheme and circuit configuration

Claim 2

An ATM switch For switching cells from N input transmission lines to M output transmission lines, where N and M are integers, comprising: N input buffers for temporarily storing cells arriving from said N input transmission lines; M output buffers for temporarily storing cells to be outputted to said M output transmission lines; and a matrix type switch formed by N input lines for transmitting the cells read out from the input buffers, M output lines for transmitting the cells to be written into the output buffers, and N×M crosspoints located at intersections of the input lines and the output lines, where each crosspoint at an intersection of one input line and one output line carries out an arbitration operation in which a cell arriving from an upper stream side of said one output line is passed to a lower stream side of said one output line with a higher priority than a cell arriving from said one input line, and the cell arriving from said one input line is transferred to the lower stream side of said one output line only when there is no cell arriving from the upper stream side of said one output line.

Claim 3

The ATM switch of claim 1, wherein said each crosspoint returns an acknowledge signal to one input buffer connected with said one input line when the cell arriving from said one input line is transferred to the lower stream side of said one output line.

Claim 4

The ATM switch of claim 2, wherein a reading speed of the input buffers and a writing speed of the output buffers are m times faster than a writing speed of the input buffers, where m is an integer and 1<m<N, such that said one input buffer repetitively reads out the cell to said one input line, up to m times at most within each input cell period by which the cells are written into the input buffers, until the acknowledge signal is returned from said each crosspoint.

Claim 5

The ATM switch of claim 1, wherein a cell read out operation of each input buffer is limited such that only one cell read out from said each input buffer is transferred to the output buffers within one input cell period by which the cells are written into the input buffers.

Claim 6

The ATM switch of claim 1, wherein each input buffer measures an actual queue length within itself and discards an earliest stored cell among currently stored cells when the actual queue length exceeds a prescribed threshold queue length.

Claim 7

The ATM switch of claim 1, wherein each crosspoint further comprises: selector means for selectively outputting one of the cell arriving from said one input line and the cell arriving from the upper stream side of said one output line to the lower stream side of said one output line; address filter means for outputting an output signal indicating whether the cell arriving from said one input line has an output destination address coinciding with a prescribed destination address specified for said each crosspoint; and arbitration circuit means for generating a selector control signal for controlling a selection operation of the selector means according to the output signal of the address filter means and a frame signal for the cell arriving from the upper stream side of said one output line.

Claim 8

The ATM switch of claim 6, wherein the arbitration circuit means further comprises: AND gate means for outputting a product of the output signal of the address filter means and a negation of the frame signal for the cell arriving from the upper stream side of said one output line; and latch means for outputting the selector control signal to the selector means according to the product outputted by the AND gate means.

Claim 9

The ATM switch of claim 7, wherein the latch means has an S terminal for receiving the product outputted by the AND gate means, and an R terminal for receiving one of a frame signal for the cell arriving from said one input line and an externally supplied input cell period by which the cells are written into the input buffers.

Claim 10

The ATM switch of claim 6, wherein the arbitration circuit means also outputs the selector control signal to one input buffer connected with said one input line as an acknowledge signal when the cell arriving from said one input line is transferred to the lower stream side of said one output line.

Claim 11

The ATM switch of claim 1, wherein each crosspoint further comprises: address filter means for outputting an output signal indicating whether the cell arriving from said one input line has an output destination address coinciding with a prescribed destination address specified for said each crosspoint; first AND gate means for outputting a product of the output signal of the address filter means and a negation of the frame signal for the cell arriving from the upper stream side of said one output line; second AND gate means for outputting a product of the cell arriving from said one input line and the product outputted by the first AND gate means; first OR gate means for outputting one of the product outputted by the second AND gate means and the cell arriving from the upper stream side of said one output line, to the lower stream side of said one output line; second OR gate means for outputting one of the output signal of the address filter means and the frame signal for the cell arriving from the upper stream side of said one output line, to the lower stream side of said one output line; and third OR gate means for outputting one of the product outputted by the first AND gate means and an acknowledge signal arriving from an adjacent crosspoint, as the acknowledge signal to be returned to one input buffer connected with said one input line.

Claim 12

The ATM switch of claim 1, wherein each output buffer is connected with one output line such that a jj-th crosspoint at an intersection of a j-th input line and a j-th output line among the crosspoints located on said one output line is set to be a most upper stream side crosspoint, where j is an integer and 1≦j≦N, 1≦j≦M.

Claim 13

The ATM switch of claim 1, wherein the crosspoints forming the matrix type switch are optical crosspoints.

Claim 14

The ATM switch of claim 12, wherein each optical crosspoint further comprises: optical filter means for outputting an output signal indicating whether a wavelength of a frame signal for the cell arriving from said one input line is within a prescribed range specified for said each optical crosspoint; optical AND fate means for outputting a product of the output signal of the optical filter means and a negation of the frame signal for the cell arriving from the upper stream side of said one output line; photonic switch means for changing a propagation direction of the cell arriving from said one input line according to the product outputted by the optical AND gate means; first optical OR gate means for outputting one of the cell arriving from said one input line whose propagation direction is changed by the photonic switch means and the cell arriving from the upper stream side of said one output line, to the lower stream side of said one output line; second optical OR gate means for outputting one of the output signal of the optical filter means and the frame signal for the cell arriving from the upper stream side of said one output line, to the lower stream side of said one output line; and third optical OR gate means for outputting one of the product outputted by the optical AND gate means and an acknowledge signal arriving from an adjacent crosspoint, as the acknowledge signal to be returned to one input buffer connected with said one input line.

Claim 17

The method of claim 14, further comprising the step of returning an acknowledge signal from said each crosspoint to one input buffer connected with said one input line when the cell arriving from said one input line is transferred to the lower stream side of said one output line.

Claim 18

The method of claim 15, wherein a reading speed of the input buffers and a writing speed of the output buffers are set to be m times faster than a writing speed of the input buffers at the forming step, where m is an integer and 1<m<N, and further comprising the step of operating said one input buffer to repetitively read out the cell to said one input line, up to m times at most within each input cell period by which the cells are written into the input buffers, until the acknowledge signal is returned from said each crosspoint at the returning step.

Claim 19

The method of claim 14, further comprising the step of operating each input buffer under a limitation that only one cell read out from said each input buffer is transferred to the output buffers within one input cell period by which the cells are written into the input buffers.

Claim 20

The method of claim 14, further comprising the step of measuring an actual queue length within each input buffer and discarding an earliest stored cell among currently stored cells when the actual queue length exceeds a prescribed threshold queue length.

Claim 21

The method of claim 14, wherein at the forming step, each output buffer is connected with one output line such that a jj-th crosspoint at an intersection of of a j-th input line and a J-th output line among the crosspoints located on said one output line is set to be a most upper stream side crosspoint, where j is an integer and 1≦j≦N, 1≦j≦M.

Claim 22

An ATM switch for switching cells from N input transmission lines to M output transmission lines, where N and M are integers, comprising: N input buffers for temporarily storing cells arriving from said N input transmission lines; M output buffers for temporarily storing cells to be outputted to said M output transmission lines; a matrix type switch formed by N input lines for transmitting the cells read out from the input buffers, M output lines for transmitting the cells to be written into the output buffers, and N×M crosspoints located at intersections of the input lines and the output lines, where each output buffer is connected with one output line such that a jj-th crosspoint at an intersection of of a j-th input line and a j-th output line is set to be a most upper stream side crosspoint among the crosspoints located on said one output line, where j is an integer and 1≦j≦N, 1≦j≦M.

Claim 23

An ATM switch for switching cells from N input transmission lines to M output transmission lines, where N and M are integers, comprising: N input buffers for temporarily storing cells arriving from said N input transmission lines; M output buffers for temporarily storing cells to be outputted to said M output transmission lines; a matrix type switch formed by N input lines for transmitting the cells read out from the input buffers, M output lines for transmitting the cells to be written into the output buffers, and N×M crosspoints located at intersections of the input lines and the output lines, where each output buffer is connected with one output line such that a jj-th crosspoint at an intersection of of a j-th input line and a j-th output line is set to be a most upper stream side crosspoint among the crosspoints located on said one output line, where j is an integer and 1≦j≦N, 1≦j≦M.

Claim 24

The ATM switch of claim 20, wherein each crosspoint at an intersection of one input line and one output line carries out an arbitration operation in which a cell arriving from an upper stream side of said one output line is passed to a lower stream side of said one output line with a higher priority than a cell arriving from said one input line, and the cell arriving from said one input line is transferred to the lower stream side of said one output line only when there is no cell arriving from the upper stream side of said one output line.

Claim 25

The ATM switch of claim 20, wherein each crosspoint at an intersection of one input line and one output line carries out an arbitration operation in which a cell arriving from said one input line is transferred to a lower stream side of said one output line with a higher priority than a cell arriving from an upper stream side of said one output line, and the cell arriving from the upper stream side of said one output line is passed to the lower stream side of said one output line only when there is no cell arriving from said input line.