Method of simulating hot carrier deterioration of an MOS transistor

Claim 1

A method of analyzing an integrated circuit of a semiconductor device comprising a plurality of components including an N-MOS transistor, which method comprises: operating said semiconductor device; predicting deterioration of the N-MOS transistor by simulating hot carrier deterioration; and taking corrective action in response to simulating hot carrier deterioration by isolating areas of the integrated circuit susceptible to hot carrier degradation effects; wherein said simulating hot carrier deterioration of an N-MOS transistor comprises formulas (6) and (7): F.sub.N (t)=(W·B).sup.-n ·I.sub.SUB.sup.mn ·I.sub.D.sup.(1-m)n ·t.sup.n ( 6) ΔI.sub.D /I.sub.D =(ΔI.sub.D /I.sub.D).sub.f ·F.sub.N (t) (7) where F N (t) represents a quantity of a hot carrier stress applied until a time t, W represents a width of a gate of said transistor, B represents a coefficient depending on a manufacturing condition of said transistor, I SUB represents a substrate current, I D represents a drain current, m represents an index which is deemed to be correlated to impact ionization and generation of interface energy levels, and (ΔI D /I D ) represents a rate of a variation ΔI D of said drain current at the time of expiration of a lifetime of said transistor to an initial value of said drain current I D , wherein n is not a constant but is expressed as a function n=g(V G , V D ) of a gate voltage V G and a drain voltage V D which are applied at the time of said hot carrier stress, and said function is determined by a preliminary experiment.

Claim 2

A method of analyzing an integrated circuit of a semiconductor device comprising a plurality of components including an N-MOS transistor, which method comprises: operating said semiconductor device; predicting deterioration of the N-MOS transistor by simulating hot carrier deterioration; and taking corrective action in response to simulating hot carrier deterioration by isolating areas of the integrated circuit susceptible to hot carrier degradation effects; wherein said simulating hot carrier deterioration of an N-MOS transistor comprises formulas (6) and (7): F.sub.N (t)=(W·B).sup.-n ·I.sub.SUB.sup.mn ·I.sub.D.sup.(1-m)n ·t.sup.n ( 6) ΔI.sub.D /I.sub.D =(ΔI.sub.D /I.sub.D).sub.f ·F.sub.N (t) (7) where F N (t) represents a quantity of a hot carrier stress applied until a time t, W represents a width of a gate of said transistor, B represents a coefficient depending on a manufacturing condition of said transistor, I SUB represents a substrate current, I D represents a drain current, m represents an index which is deemed to be correlated to impact ionization and generation of interface energy levels, and (ΔI D /I D ) represents a rate of a variation ΔI D of said drain current at the time of expiration of a lifetime of said transistor to an initial value of said drain current I D , wherein n is not a constant but is expressed as a function n=g(V G , V D ) of a gate voltage V G and a drain voltage V D which are applied at the time of said hot carrier stress, and said function is determined by a preliminary experiment.

Claim 9

A method of analyzing an integrated circuit of a semiconductor device comprising a plurality of components including an P-MOS transistor, which method comprises: operating said semiconductor device; predicting deterioration of the P-MOS transistor by simulating hot carrier deterioration; and taking corrective action in response to simulating hot carrier deterioration by isolating areas of the integrated circuit susceptible to hot carrier degradation effects; wherein said simulating hot carrier deterioration of a P-MOS transistor comprises formulas (20) and (21): F.sub.p (t)=B.sup.-n ·W.sup.-mn ·I.sub.G.sup.mn ·t.sup.n ( 20) ΔI.sub.D /I.sub.D =(ΔI.sub.D /I.sub.D).sub.f ·F.sub.p (t) (21) where F p (t) represents a quantity of a hot carrier stress applied until a time t, B represents a coefficient depending on a manufacturing condition of said transistor, W represents a width of a gate of said transistor, I G represents a gate current, m represents an index which is deemed to be correlated to impact ionization and generation of interface energy levels, and (ΔI D /I D ) represents a rate of a variation ΔI D of said drain current at the time of expiration of a lifetime of said transistor to an initial value of said drain current I D , wherein n is not a constant but is expressed as a function n=g(V G , V D ) of a gate voltage V G and a drain voltage V D which are applied at said time of said hot carrier stress, and said function is determined by a preliminary experiment.

Claim 10

A method of analyzing an integrated circuit of a semiconductor device comprising a plurality of components including an P-MOS transistor, which method comprises: operating said semiconductor device; predicting deterioration of the P-MOS transistor by simulating hot carrier deterioration; and taking corrective action in response to simulating hot carrier deterioration by isolating areas of the integrated circuit susceptible to hot carrier degradation effects; wherein said simulating hot carrier deterioration of a P-MOS transistor comprises formulas (20) and (21): F.sub.p (t)=B.sup.-n ·W.sup.-mn ·I.sub.G.sup.mn ·t.sup.n ( 20) ΔI.sub.D /I.sub.D =(ΔI.sub.D /I.sub.D).sub.f ·F.sub.p (t) (21) where F p (t) represents a quantity of a hot carrier stress applied until a time t, B represents a coefficient depending on a manufacturing condition of said transistor, W represents a width of a gate of said transistor, I G represents a gate current, m represents an index which is deemed to be correlated to impact ionization and generation of interface energy levels, and (ΔI D /I D ) represents a rate of a variation ΔI D of said drain current at the time of expiration of a lifetime of said transistor to an initial value of said drain current I D , wherein n is not a constant but is expressed as a function n=g(V G , V D ) of a gate voltage V G and a drain voltage V D which are applied at said time of said hot carrier stress, and said function is determined by a preliminary experiment.