Image data partitioning circuit for parallel image decoding system

Claim 1

An image data partitioning circuit for use in an image decoding system having N decoding modules for decompressing a variable length coded image in parallel, wherein the variable length coded image includes M number of horizontally sliced data thereof, each of the sliced data having a different bit length, and N and M being integers larger than 1, which comprises: N buffer means for storing the variable length coded image, wherein each of the buffer means is coupled to its corresponding decoding module and has fixed storage locations for storing M/N number of the horizontally sliced data; first detecting means for detecting a starting position of the horizontally sliced data and generating a starting position detection signal; and partitioning means, responsive to the starting position detection signal, for sequentially providing the horizontally sliced data to a preceding buffer means and for detecting ((M/N)i+1)st horizontally sliced data to provide the horizontally sliced data to a next buffer means, thereby sequentially providing M/N horizontally slice data to the N buffer means, wherein i is 0 or an integer from 1 to N, said partitioning means including: storage means for temporarily storing the horizontally sliced data and, in response to a clock signal, for simultaneously providing a predetermined number of bits contained in the horizontally sliced data to the buffer means; counting means for counting a bits contained in the horizontally sliced data to generate the clock signal when said counted value reaches the predetermined number; boundary detection means for sensing the start position detection signal to generate a boundary detection signal when the ((M/N)i+1)st horizontally sliced data is detected and for detecting initial bits of the ((M/N)i+1)st horizontally sliced data contained in the predetermined number of bits to add a value representative of the number of the initial bits to the counted value; and means, in response to the clock signal, for providing a buffer write signal to the buffer means and, in response to the boundary detection signal and the clock signal, for providing the buffer write signal to the next buffer means.