US5504458A
Expired / Lapsed
US
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CMOS class AB amplifier for driving capacitive and resistive loads
Assignee: Apple Inc
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Filing: 1994-09-30
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Granted: 1996-04-02
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Expires: 2014-09-30
Abstract
Abstract The class AB amplifier is configured to provide low quiescent current while achieving high internal switching rates. The buffer is connected to a large external capacitance which provides external compensation. The amplifier includes an input stage which converts differential voltages to current. An output stage provides an output current and also provides a feedback current into the input stage. A biasing network provides voltage for biasing various nodes within the amplifier. Cross-coupling is provided within the output stage for achieving a low quiescent current. A pair of current limiting circuits, one for p-channel element and another for n-channel elements, is also provided.
Inventors
- 👤 Roger Van Brunt
- 👤 Florin Oprescu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 16:10
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/30; H03F3/3001
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
219 words
An amplifier comprising: an input stage for converting a differential between a pair of input voltages into a current, said input stage having p-channel and n-channel transistors providing a differential output; an output stage for providing an output voltage, said output stage having first and second p-channel transistors, and first and second n-channel transistors; wherein said p-channel transistor of said input stage, said first p-channel transistor of said output stage, said first n-channel transistor of said output stage, and said n-channel transistor of said input stage are connected in series between a high voltage source and a ground; said second p-channel and n-channel transistors of said output stage are connected in series between said high voltage source and said ground; and said first and second p-channel and n-channel transistors of said output stage are cross-coupled with a drain of said first p-channel transistor of said output stage connected to a gate of said second n-channel transistor of said output stage and with a drain of said first n-channel transistor of said output stage connected to a gate of said second p-channel transistor of said output stage; and wherein sizes of said transistors are selected to provide a net amplification of an input differential voltage to said output voltage and to provide a stable quiescent output of about zero volts.
Claim 2
Dependent Claim
219 words
An amplifier comprising: an input stage for converting a differential between a pair of input voltages into a current, said input stage having p-channel and n-channel transistors providing a differential output; an output stage for providing an output voltage, said output stage having first and second p-channel transistors, and first and second n-channel transistors; wherein said p-channel transistor of said input stage, said first p-channel transistor of said output stage, said first n-channel transistor of said output stage, and said n-channel transistor of said input stage are connected in series between a high voltage source and a ground; said second p-channel and n-channel transistors of said output stage are connected in series between said high voltage source and said ground; and said first and second p-channel and n-channel transistors of said output stage are cross-coupled with a drain of said first p-channel transistor of said output stage connected to a gate of said second n-channel transistor of said output stage and with a drain of said first n-channel transistor of said output stage connected to a gate of said second p-channel transistor of said output stage; and wherein sizes of said transistors are selected to provide a net amplification of an input differential voltage to said output voltage and to provide a stable quiescent output of about zero volts.
Claim 3
Dependent Claim
42 words
The amplifier of claim 1, wherein said output stage also includes third p-channel and n-channel transistors connected, in series, between a drain of said second p-channel transistor of said output stage and a drain of said second n-channel of said output stage.
Claim 4
Dependent Claim
113 words
The amplifier of claim 2, further including a biasing stage having a first, second and third p-channel transistors connected in series between the high voltage and the ground; and first and second n-channel transistors connected in series between a biasing current source and ground; and wherein a gate of said second p-channel transistor of said biasing stage is connected to a gate of said first p-channel transistor of said output stage and a gate of said first n-channel transistor of said biasing stage is connected to a gate of said first n-channel transistor of said output stage; and gates of said first and second n-channel transistors of said biasing stage are connected together.
Claim 5
Dependent Claim
11 words
The amplifier of claim 1, further including a current limiting network.
Claim 6
Dependent Claim
14 words
The amplifier of claim 1 connected to an external capacitor through said output line.
Claim 7
Dependent Claim
109 words
A Class AB amplifier comprising: input and output lines; an input stage having first and second inputs for receiving voltage signals and a differential output for generating current signals proportional to a difference between the voltage signals received at said first and second inputs, said first and second inputs being coupled respectively to said input and output lines; and an output stage having first and second inputs, said first and second inputs of said output stage being coupled directly to said differential output of said input stage, said first and second input-of said output stage also being coupled to said output line via two pairs of cross-coupled transistor devices.
Claim 8
Dependent Claim
109 words
A Class AB amplifier comprising: input and output lines; an input stage having first and second inputs for receiving voltage signals and a differential output for generating current signals proportional to a difference between the voltage signals received at said first and second inputs, said first and second inputs being coupled respectively to said input and output lines; and an output stage having first and second inputs, said first and second inputs of said output stage being coupled directly to said differential output of said input stage, said first and second input-of said output stage also being coupled to said output line via two pairs of cross-coupled transistor devices.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-02 | 1999-10-02 | 2000-04-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-02 | 2003-10-02 | 2004-04-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-02 | 2007-10-02 | 2008-04-02 | $7700.00 | Window Closed / Lapsed |